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Benjamin R Sloan

from Dallas, TX
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Related to:
Jose S BalderasZane A Condo, 44Bradley T Sloan, 71Chelsea R Sloan, 36Chelsea K SloanIsabel OrtegaConnie BalderasAshley S Condo, 41Brandon A Sloan, 32Samantha M Sloan, 34Barbara L Sloan, 64Hayley R Sloan, 33
Connected to:
Adrian H Sloan, 49Anterio T Sloan, 32Arlene K Sloan, 70Asteria C Sloan, 71Barclay C Sloan, 98Boyce Sloan, 97Brooke V Sloan, 36Caylin E Sloan, 28Chanpagne A Sloan, 32Charline Sloan, 68

Benjamin Sloan Phones & Addresses

  • Dallas, TX

Resumes

Resumes

Benjamin Sloan Photo 1

Benjamin Sloan

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Location:
United States
Education:
Metropolitain Career Center 2009 - 2010
Associate in Specialized Computer Hardware, Computer Science
Benjamin Sloan Photo 2

Ceo At Bone Quality, Llc

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Location:
Dallas/Fort Worth Area
Industry:
Medical Devices

Business Records

Name / Title
Company / Classification
Phones & Addresses
Benjamin Chad Sloan
BCS TRUCKING LLC
Benjamin J. Sloan
Governing
BONE QUALITY, LLC
Mfg Measuring/Controlling Devices
7107 Churchill Way, Dallas, TX 75230
5548 Riverton Ct, Plano, TX 75093
5545 Riverton Ct, Plano, TX 75093
(214) 236-3399

Publications

Us Patents

Selective Diffusion And Etching Method For Isolation Of Integrated Logic Circuit

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US Patent:
41371097, Jan 30, 1979
Filed:
Feb 3, 1977
Appl. No.:
5/765325
Inventors:
James G. Aiken - Richardson TX
Benjamin J. Sloan - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21302
H01L 2176
US Classification:
148175
Abstract:
An integrated injection logic circuit, wherein the inverted, multi-collector transistor of each cell includes active base regions separated by dielectric isolation, and wherein a heavily-doped channel-stop layer is selectively located along the sidewalls of the isolation, to prevent collector-to-emitter surface inversion leakage. The isolated geometry substantially reduces parasitic capacitance between the substrate and the extrinsic base, thereby increasing the switching speed of the device.

Process For Fabricating Integrated Circuits Utilizing Ion Implantation

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US Patent:
39335283, Jan 20, 1976
Filed:
Jul 2, 1974
Appl. No.:
5/485199
Inventors:
Benjamin Johnston Sloan - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21265
US Classification:
148 15
Abstract:
A self-aligning process for fabrication of integrated circuits utilizing ion implantation to effect doping. A composed masking technique is used to define self-aligned areas in a silicon oxide layer for definition of isolation, base, resistor and collector contact regions. Only two oxide removal steps are required for isolation through emitter process steps, and the process uses the silicon oxide layer and photoresist material for implantation masking. Formation of the emitter region by ion implantation and by diffusion are described.

Integrated Logic Circuit And Method Of Fabrication

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US Patent:
40750396, Feb 21, 1978
Filed:
Aug 30, 1976
Appl. No.:
5/719024
Inventors:
Benjamin Johnston Sloan - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2126
US Classification:
148 15
Abstract:
An integrated injection logic circuit having improved operating characteristics is provided, comprising an inverted, multiple-collector transistor having base regions characterized by a central active portion surrounded by a heavily-doped extrinsic base region to which the base contact is made. Using ion implantation, each active portion of the base region is provided with a dopant concentration which increases with distance from the collector junction, thereby increasing transistor speed and gain. The extrinsic portion of the base reduces series resistance for multicollector transistors, provides heavy doping at the surface for good ohmic base contacts; and most importantly, defines the active emitter-base regions. The effective or "active" collector-to-emitter area ratio of the device is improved by more than 50:1 compared with prior devices.

Process For Fabricating Dielectrically Isolated Semiconductor Components Of An Integrated Circuit

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US Patent:
39381765, Feb 10, 1976
Filed:
Sep 24, 1973
Appl. No.:
5/400492
Inventors:
Benjamin Johnston Sloan - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2712
US Classification:
357 49
Abstract:
Disclosed is a method of fabricating dielectrically isolated semiconductor components of an integrated circuit, and the semiconductor component formed by this method, each component having a plurality of high conductivity regions extending from the interior of said component to the surface thereof to provide high conductivity paths to selected semiconductor regions of the component.

Npm Anti-Saturation Clamp For Npn Logic Gate Transistor

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US Patent:
44059345, Sep 20, 1983
Filed:
Apr 13, 1981
Appl. No.:
6/253444
Inventors:
Benjamin J. Sloan - Garland TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2948
US Classification:
357 15
Abstract:
A bipolar logic gate formed in an isolated N-type epitaxial layer in an integrated circuit device includes a normally operated vertical NPN switch transistor clamped by an inversely operated NPM clamp transistor. The base of the clamp transistor is formed by a high energy boron ion implant into a portion of the N-type epitaxial layer extending through the P-type base of the switch transistor. Multiple outputs are provided by Schottky barrier diodes formed on the N-type epitaxial layer.

Input Buffer For Integrated Injection Logic Circuits

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US Patent:
41807499, Dec 25, 1979
Filed:
Jul 18, 1977
Appl. No.:
5/816408
Inventors:
Benjamin J. Sloan - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H03K 1908
US Classification:
307299B
Abstract:
An input buffer gate for integrated injection logic (I. sup. 2 L) circuits, including a multiple-collector transistor wherein a first collector is electrically common with the base thereof, a second (Schottky) collector is connected to receive an input signal, and a third collector which drives internal I. sup. 2 L gates. The buffer has a high input breakdown voltage, virtually no input capacitance, power-up/power-down capability at logic "1" and virtually no input current at logic "0", very low storage time, and an input "1" threshold of about 0. 5 volts.
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Benjamin R Sloan from Dallas, TX Get Report