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Carlos A Tokunaga

from Beaverton, OR
Age ~46
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Also known as:
Carlos A Trs, Carlos Tokunaga Tanaka
Related to:
Masato TokunagaStacie Oshiro, 39Kristy A OMichael Oshiro, 73Kristy A Oshiro, 41
Connected to:
Atsuko Tokunaga, 62Donald H Tokunaga, 107Karen K Tokunaga, 64Keiji Tokunaga, 49Mackenzie N Tokunaga, 38Toshiko Tokunaga, 94Wayne T Tokunaga, 62Yoko Tokuno, 54Miles M Tokunow, 37Crystal Tokushige, 40

Carlos Tokunaga Phones & Addresses

  • Beaverton, OR
  • Ann Arbor, MI
  • 16238 NW Somerset Dr, Beaverton, OR 97006

Work

Company: Intel Dec 2008 Position: Research scientist

Education

Degree: Ph.D. School / High School: University of Michigan 2003 to 2008 Specialities: Electrical Engineering

Skills

Verilog • Semiconductors • Computer Architecture • Circuit Design • Vlsi • Very Large Scale Integration • Simulations • Asic • Integrated Circuits • Ic • Perl • Soc • Cmos • C • Microprocessors • R&D • Application Specific Integrated Circuits • System on A Chip • Matlab • Research • Fpga • Eda • Vhdl

Languages

English • Spanish

Industries

Semiconductors

Resumes

Resumes

Carlos Tokunaga Photo 1

Research Scientist

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Location:
Hillsboro, OR
Industry:
Semiconductors
Work:
Intel since Dec 2008
Research Scientist
Intel Feb 2008 - Jun 2008
Intern
University of Michigan 2005 - 2008
Graduate Student Research Assistant
Intel Sep 2006 - Dec 2006
Intern
Education:
University of Michigan 2003 - 2008
Ph.D., Electrical Engineering Universidad de Los Andes 1996 - 2001
BS, Electronics Engineering
Skills:
Verilog
Semiconductors
Computer Architecture
Circuit Design
Vlsi
Very Large Scale Integration
Simulations
Asic
Integrated Circuits
Ic
Perl
Soc
Cmos
C
Microprocessors
R&D
Application Specific Integrated Circuits
System on A Chip
Matlab
Research
Fpga
Eda
Vhdl
Languages:
English
Spanish

Publications

Us Patents

Random Number Generator

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US Patent:
8346832, Jan 1, 2013
Filed:
Jul 19, 2007
Appl. No.:
11/826996
Inventors:
Trevor Nigel Mudge - Ann Arbor MI, US
David Theodore Blaauw - Ann Arbor MI, US
Carlos Alfonso Tokunaga - Ann Arbor MI, US
Assignee:
The Regents of the University of Michigan - Ann Arbor MI
International Classification:
G06F 1/02
G06F 7/58
US Classification:
708250
Abstract:
A circuit for generating a random output value is disclosed that comprises: a bistable circuit having two stable states in which a 0 or a 1 is output and having a balanced metastable state in which a floating value between 0 and 1 is output, said bistable circuit resolving from said metastable state to one of said stable states on being switched on, said state depending on a voltage level at a port on said bistable circuit; a voltage level control circuit for controlling a voltage level at said port on said bistable circuit; a time measuring circuit for measuring a switching time taken for said bistable circuit to switch from said metastable state to one of said stable states following switch on; and control logic for controlling said time measuring circuit, said voltage level control circuit and a switching off and on of said bistable circuit, said control logic being adapted to perform a following sequence: control said voltage level control circuit to set a predetermined voltage level at said port on said bistable circuit, switch said bistable circuit on, detect a measured switching time, and turn said bistable circuit off and if said measured switching time is longer than a predetermined value, output said resolved stable state of said bistable circuit as said random output value.

Isolation Circuitry And Method For Hiding A Power Consumption Characteristic Of An Associated Processing Circuit

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US Patent:
20100194205, Aug 5, 2010
Filed:
Feb 3, 2009
Appl. No.:
12/320747
Inventors:
Carlos Alfonso Tokunaga - Hillsboro OR, US
David Theodore Blaauw - Ann Arbor MI, US
Assignee:
The Regents of the University of Michigan - Ann Arbor MI
International Classification:
G05F 3/02
US Classification:
307100
Abstract:
An isolation circuitry and method are provided for coupling between a power supply and processing circuitry in order to provide power to the processing circuitry whilst hiding a power consumption characteristic of that processing circuitry. The isolation circuitry comprises a plurality of sub-circuits, with each sub-circuit comprising a capacitor, a first switch configured to provide a first connection between the capacitor and the power supply, a second switch configured to provide a second connection between the capacitor and the processing circuitry, and a third switch configured to provide a third connection across the capacitor to partially discharge the capacitor. Control circuitry controls the plurality of sub-circuits, such that within each sub-circuit the first switch, second switch and third switch are placed in an active state in a repeating sequence. Each of the plurality of sub-circuits further comprises a comparator configured to place the third switch in an open state when a predetermined non-zero voltage difference across the capacitor is reached during the active state of the third switch. By such an approach, it is ensured that the voltage across the comparator at the end of the discharge operation is always the same irrespective of the voltage present at the start of the discharge operation. As a result, the power consumption characteristic of the processing circuitry is entirely hidden by the isolation circuitry. Further, the isolation circuitry of the present invention provides a particular power efficient mechanism for hiding the power consumption characteristic of the processing circuitry.

Self-Contained, Path-Level Aging Monitor Apparatus And Method

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US Patent:
20130285685, Oct 31, 2013
Filed:
Sep 28, 2011
Appl. No.:
13/976931
Inventors:
Keith A. Bowman - Hillsboro OR, US
Carlos Tokunaga - Hillsboro OR, US
James W. Tschanz - Portland OR, US
International Classification:
G01R 31/317
US Classification:
3247503
Abstract:
An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a separate aging path with driving and receiving flip flops (FFs) and a tunable replica circuit (TRC) to enable measurements of single-transition DC-stressed path delay that only propagates through stressed transistors or other circuit element(s). A finite state machine (FSM) in the aging monitor circuit is configured to adjust a frequency of a clock signal output by a digitally controlled oscillator (DCO) in response to an error signal output by the receiving FF. The error signal is generated in response to single transition DC-stressed path delay, and therefore enables the adjustment of the frequency of the clock signal to correspond to an amount or effect of the delay.

Circuits And Methods For Voltage Detection In Integrated Circuits

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US Patent:
20200226295, Jul 16, 2020
Filed:
Mar 25, 2020
Appl. No.:
16/829582
Inventors:
- Santa Clara CA, US
Sriram Vangal - Portland OR, US
Patrick Koeberl - Portland OR, US
Miguel Bautista Gabriel - Portland OR, US
James Tschanz - Portland OR, US
Carlos Tokunaga - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 21/75
H03K 5/00
H03K 3/037
H03K 19/21
H01L 23/00
G06F 11/07
G01R 19/165
Abstract:
A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

Countermeasures Against Hardware Side-Channel Attacks On Cryptographic Operations

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US Patent:
20190318130, Oct 17, 2019
Filed:
Jun 28, 2019
Appl. No.:
16/456308
Inventors:
- Santa Clara CA, US
Debayan Das - West Lafayette IN, US
Carlos Tokunaga - Hillsboro OR, US
Avinash L. Varna - Chandler AZ, US
Joseph Friel - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 21/72
G06F 21/64
G06F 21/12
Abstract:
Embodiments are directed to countermeasures against hardware side-channel attacks on cryptographic operations. An embodiment of an apparatus includes multiple crypto cores; and a current source including multiple current source blocks, the current source blocks including a respective current source block associated with each of the crypto cores, and wherein the current sources blocks are switchable to switch on a current source block associated with each active core of the multiple crypto cores and to switch off a current source associated with each inactive core of the multiple cryptographic cores.

Adaptive Voltage System For Aging Guard-Band Reduction

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US Patent:
20180287592, Oct 4, 2018
Filed:
Apr 3, 2017
Appl. No.:
15/477913
Inventors:
- Santa Clara CA, US
Jaydeep Kulkarni - Portland OR, US
Carlos Tokunaga - Hillsboro OR, US
Muhammad Khellah - Tigard OR, US
James Tschanz - Portland OR, US
International Classification:
H03K 3/011
H03K 3/012
G11C 11/419
G06F 1/32
Abstract:
An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.

Voltage Level Shifter Monitor With Tunable Voltage Level Shifter Replica Circuit

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US Patent:
20180191347, Jul 5, 2018
Filed:
Dec 29, 2016
Appl. No.:
15/394296
Inventors:
- SANTA CLARA CA, US
Jaydeep P. Kulkarni - Portland OR, US
Carlos Tokunaga - Hillsboro OR, US
Minki Cho - Hillsboro OR, US
Pascal A. Meinerzhagen - Hillsboro OR, US
Muhammad M. Khellah - Tigard OR, US
International Classification:
H03K 19/0185
H03K 19/21
Abstract:
Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.

Retention Minimum Voltage Determination Techniques

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US Patent:
20180166145, Jun 14, 2018
Filed:
Dec 8, 2016
Appl. No.:
15/373048
Inventors:
- Santa Clara CA, US
Jaydeep KULKARNI - Portland OR, US
Carlos TOKUNAGA - Hillsboro OR, US
Muhammad KHELLAH - Tigard OR, US
James TSCHANZ - Portland OR, US
International Classification:
G11C 29/12
G11C 5/14
G11C 11/417
Abstract:
An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage cells are to receive a supply voltage. The semiconductor chip includes supply voltage retention circuitry. The supply voltage retention circuitry is to determine a level of the supply voltage at which the storage cells are able to retain their respective data. The supply voltage retention circuitry is to receive the supply voltage during a stress mode of the supply voltage retention circuitry. The supply voltage retention circuitry is to more weakly retain its stored information than the storage cells during a measurement mode at which the level is determined.
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Carlos A Tokunaga from Beaverton, OR, age ~46 Get Report