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David W Knebelsberger

from Tempe, AZ
Age ~66
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Also known as:
Jeananne M Knebelsberger, David A Knebelsberger, David E Knebelsberger, Jeananne Anne Knebelsberger, David William Knebelsberger, Jean A Knebelsberger, Jean-Anne M Knebelsberger, Jean R, Dave Knebelsberger, Jean Anne G
Related to:
Joseph M Knebelsberger, 36Rachel A Knebelsberger, 35J R, 63Rebecca Jo KnebelsbergerJ Knebelsberger, 63Joseph M KnebelsbergerDaniel KnebelsbergerJean-Anne E Knebelsberger, 67Thomas D Knebelsberger, 31
Connected to:
Francis G Knebels, 77Terrie L Knebelsberger, 64Eleanor K Knebl, 103Lauren A Knebl, 35Siegmar M Knebl, 49Christopher C Knebusch, 47Francis L Knece, 96Jessica D Knece, 41Chris J Knechel, 44Tracy A Knechel, 52

David Knebelsberger Phones & Addresses

  • Tempe, AZ
  • Chandler, AZ
  • Salt Lake City, UT
  • Maricopa, AZ
  • West Jordan, UT
  • Sacramento, CA
  • 2116 S Bonarden Ln, Tempe, AZ 85282 (480) 235-4865

Work

Position: Service Occupations

Emails

d***[email protected]

Publications

Us Patents

Very Small Swing High Performance Cmos Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme

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US Patent:
6519204, Feb 11, 2003
Filed:
Sep 27, 2001
Appl. No.:
09/964971
Inventors:
Mark Slamowitz - Chandler AZ
Douglas D. Smith - Mesa AZ
David W. Knebelsberger - Tempe AZ
Gregory Djaja - Phoenix AZ
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 800
US Classification:
36523005, 365154
Abstract:
Devices and methods relating to a multi-port register file memory including a plurality of storage elements in columns are disclosed. The storage elements are arranged in rows and columns and store data. At least one read port is coupled to each of the storage elements and a sensing device is coupled to the read port. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A pair of series transistors coupled together act as the read port while a column mux circuit is coupled to each column and the sensing device. The sensing device includes two inverters comprising input offset and gain stages. An offset device biases the local bitlines at a voltage close to the sense amplifier trip point.

Very Small Swing High Performance Asynchronous Cmos Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme

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US Patent:
6639866, Oct 28, 2003
Filed:
Nov 3, 2001
Appl. No.:
10/012858
Inventors:
Mark Slamowitz - Chandler AZ
Douglas D. Smith - Mesa AZ
David W. Knebelsberger - Tempe AZ
Myron Buer - Gilbert AZ
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 800
US Classification:
36523005, 365154, 36518907, 365207
Abstract:
The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

Very Small Swing High Performance Asynchronous Cmos Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme

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US Patent:
6822918, Nov 23, 2004
Filed:
Oct 6, 2003
Appl. No.:
10/679547
Inventors:
Mark Slamowitz - Chandler AZ
Douglas D. Smith - Mesa AZ
David W. Knebelsberger - Tempe AZ
Myron Buer - Gilbert AZ
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 700
US Classification:
365207, 36518907
Abstract:
The present invention relates to a method for improving speed and increasing performance in a multi-port register file memory or SRAM including at least one storage element and other circuitry that operate synchronously or asynchronously. The method comprises differentially sensing a small voltage swing in the multi-port memory using a two-stage analog-style sense amplifier including at least one trip-level-shifted inverter device.

Very Small Swing High Performance Cmos Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme

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US Patent:
6903996, Jun 7, 2005
Filed:
Jan 10, 2003
Appl. No.:
10/340066
Inventors:
Mark Slamowitz - Chandler AZ, US
Douglas D. Smith - Mesa AZ, US
David W. Knebelsberger - Tempe AZ, US
Gregory Djaja - Phoenix AZ, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C008/00
US Classification:
36523005, 365154
Abstract:
The present invention relates to storage element. At least one read port is coupled to the storage element and a sensing device is coupled to the read port, where the read port is coupled to the storage element in an isolated manner. The sensing device is adapted to sense a small voltage swing. The sensing device includes two inverters comprising input offset and gain stages.

Very Small Swing High Performance Asynchronous Cmos Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme

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US Patent:
7251175, Jul 31, 2007
Filed:
Nov 23, 2004
Appl. No.:
10/996140
Inventors:
Mark Slamowitz - Chandler AZ, US
Douglas D. Smith - Mesa AZ, US
David W. Knebelsberger - Tempe AZ, US
Myron Buer - Gilbert AZ, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 7/06
US Classification:
365207, 365154, 36523005
Abstract:
The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously, and a method of making the multi-port register file memory. The storage elements are arranged in N rows and M columns and store data, each column having at least one output channel or circuit. Two read port pairs are coupled to each of the storage elements and a plurality of differential sensing devices or circuits. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and at least one of the sensing device. The method of forming the multi-port register file memory comprises determining the number of storage elements and arranging the storage elements in the N rows and M columns, each column having an output channel.

Very Small Swing High Performance Asynchronous Cmos Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme

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US Patent:
7639549, Dec 29, 2009
Filed:
Jul 12, 2007
Appl. No.:
11/777054
Inventors:
Mark Slamowitz - Chandler AZ, US
Douglas D. Smith - Mesa AZ, US
David W. Knebelsberger - Tempe AZ, US
Myron Buer - Gilbert AZ, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 7/00
US Classification:
36518911, 365154, 365207, 36523005
Abstract:
The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

Very Small Swing High Performance Asynchronous Cmos Static Memory (Multi-Port Register File) With Power Reducing Column Multiplexing Scheme

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US Patent:
7986570, Jul 26, 2011
Filed:
Nov 12, 2009
Appl. No.:
12/617570
Inventors:
Mark Slamowitz - Chandler AZ, US
Douglas D. Smith - Mesa AZ, US
David W. Knebelsberger - Tempe AZ, US
Myron Buer - Gilbert AZ, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 7/00
US Classification:
36518911, 365154, 365207, 36523005
Abstract:
The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously. The storage elements are arranged in rows and columns and store data. Two read port pairs are coupled to each of the storage elements and a differential sensing device or circuit. The read port is coupled to the storage elements in an isolated manner, enabling a plurality of cells to be arranged in such rows and columns. The sensing device is adapted to sense a small voltage swing. A column mux circuit is coupled to each column and the sensing device. Performance is not degraded unusually as the power supply voltage is reduced due to bus drop or inductive effects.

Read-Only Memory (Rom) Bitcell, Array, And Architecture

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US Patent:
8406031, Mar 26, 2013
Filed:
Dec 16, 2010
Appl. No.:
12/970416
Inventors:
Myron Buer - Savage MN, US
Dechang Sun - Eden Prairie MN, US
Duane Jacobson - Phoenix AZ, US
David William Knebelsberger - Tempe AZ, US
Jan LeClair - Prior Lake MN, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
G11C 17/08
US Classification:
365104, 36518905
Abstract:
Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.
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David W Knebelsberger from Tempe, AZ, age ~66 Get Report