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Dwayne K Kreipl

from Boise, ID
Age ~56
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Also known as:
Dwayne Karl Kreipl, Dwayne E Kreipl, Dwayne Karl Keipl, Dwain K Kreipl, Dwayne K Kriepl
Phone and address:
1002 Bannock St, Boise, ID 83712
(208) 345-3453
Related to:
William A LarsenKirk S Larsen, 57Beverly H Kreipl, 80Kory L Kreipl, 47Elisabeth A Boren, 55Kreipl Lara, 48Karl B Kreipl, 86
Connected to:
Brian M Kreis, 49Charles R Kreis, 64Curtis R Kreis, 61Glen O Kreis, 81Heidi S Kreis, 41Ingrid B Kreis, 63Melinda A Kreis, 48Philip T Kreis, 59Earl J Kreisa, 85Ann Kreisberg, 85

Dwayne Kreipl Phones & Addresses

  • 1002 Bannock St, Boise, ID 83712 (208) 345-3453 (208) 342-4368
  • Brooklyn, NY
  • Millville, UT
  • 1002 E Bannock St, Boise, ID 83712 (208) 345-3453

Work

Company: Clearwater analytics Aug 2019 Position: Head of enterprise data management and reporting

Education

Degree: Bachelors, Bachelor of Science In Electrical Engineering School / High School: Utah State University 1990 to 1995 Specialities: Electrical Engineering

Skills

Semiconductors • Analysis • Data Analysis • Testing • Debugging • Management • R&D • Product Development • Team Building • Electronics • Leadership • Project Management • Product Engineering • Start Ups • Research and Development • Sql • Silicon • Problem Solving • Negotiation • Manufacturing • Cmos • Ic

Languages

Spanish

Emails

l***[email protected]

Industries

Financial Services

Resumes

Resumes

Dwayne Kreipl Photo 1

Director Of Data Management

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Location:
Boise, ID
Industry:
Financial Services
Work:
Clearwater Analytics
Head of Enterprise Data Management and Reporting
Clearwater Analytics Jan 2019 - Jul 2019
Director Strategic Initiatives
Clearwater Analytics Jan 2019 - Jul 2019
Director of Data Management
Micron Inc Jan 2007 - Feb 2008
Senior Imaging Product Engineer
Micron Inc Jun 2004 - Jan 2007
R and D Product Engineering Supervisor
Education:
Utah State University 1990 - 1995
Bachelors, Bachelor of Science In Electrical Engineering, Electrical Engineering
Skills:
Semiconductors
Analysis
Data Analysis
Testing
Debugging
Management
R&D
Product Development
Team Building
Electronics
Leadership
Project Management
Product Engineering
Start Ups
Research and Development
Sql
Silicon
Problem Solving
Negotiation
Manufacturing
Cmos
Ic
Languages:
Spanish

Publications

Us Patents

Recessed Gate Dielectric Antifuse

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US Patent:
7795094, Sep 14, 2010
Filed:
Sep 2, 2004
Appl. No.:
10/933161
Inventors:
Dwayne Kreipl - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/336
H01L 21/3205
US Classification:
438259, 438281, 438301, 438589, 257E21592, 257E21655, 257E21666
Abstract:
A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.

Recessed Gate Dielectric Antifuse

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US Patent:
7833860, Nov 16, 2010
Filed:
Jul 25, 2006
Appl. No.:
11/492620
Inventors:
Dwayne Kreipl - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 21/336
H01L 21/3205
H01L 21/311
US Classification:
438259, 438270, 438281, 438306, 438589, 438591, 438703, 257E23147, 257E21428
Abstract:
A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.

Antifuse Programming Circuit With Snapback Select Transistor

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US Patent:
7915916, Mar 29, 2011
Filed:
Jun 1, 2006
Appl. No.:
11/421614
Inventors:
William J. Wilcox - Meridian ID, US
James C. Davis - Boise ID, US
Dwayne K. Kreipl - Boise ID, US
Michael B. Pearson - Boise ID, US
Assignee:
Micron Technology, Inc. - Bosie ID
International Classification:
G06F 7/38
H03K 19/173
H03K 19/094
G11C 17/00
G11C 17/18
US Classification:
326 38, 365 96, 3652257, 326 37, 326 49
Abstract:
An antifuse circuit includes a terminal, an antifuse, and a select transistor. The antifuse is coupled to the terminal and has an associated program voltage. The select transistor is coupled to the antifuse and has a gate terminal coupled to receive a first select signal. The select transistor operates in a snapback mode of operation in response to an assertion of the first select signal and the program voltage at the terminal.

Recessed Gate Dielectric Antifuse

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US Patent:
8076673, Dec 13, 2011
Filed:
Aug 13, 2010
Appl. No.:
12/856240
Inventors:
Dwayne Kreipl - Boise ID, US
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
H01L 29/04
H01L 23/52
US Classification:
257 50, 257209, 257530, 257E23147
Abstract:
A recessed dielectric antifuse device includes a substrate and laterally spaced source and drain regions formed in the substrate. A recess is formed between the source and drain regions. A gate and gate oxide are formed in the recess and lightly doped source and drain extension regions contiguous with the laterally spaced source and drain regions are optionally formed adjacent the recess. Programming of the recessed dielectric antifuse is performed by application of power to the gate and at least one of the source region and the drain region to breakdown the dielectric, which minimizes resistance between the gate and the channel.

Fluidkinetic Energy Converter

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US Patent:
20110089702, Apr 21, 2011
Filed:
Dec 22, 2010
Appl. No.:
12/977014
Inventors:
David Boren - Boise ID, US
Jonathan Boren - Boise ID, US
Dwayne Kreipl - Boise ID, US
International Classification:
F03D 9/00
F01D 25/24
US Classification:
290 55, 4151821
Abstract:
A fluidkinetic energy converter includes a passageway-filled enclosure. Turbines are mounted in the passageways and fluid flow may be concentrated on subparts of the turbines by inner fluid flow deflectors or dividers. The energy converter enclosure can include dividers at both inlets and outlets in order to be adaptable for either river or tidal environments. Notably, apart from the turbines and energy generating components, the enclosure may be implemented such as to have no moving parts, thereby reducing complexity, cost, and weight.

Current Monitor For Field Emission Displays

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US Patent:
59400528, Aug 17, 1999
Filed:
Jan 15, 1997
Appl. No.:
8/783044
Inventors:
Dwayne Kreipl - Boise ID
Glenn Piper - Boise ID
Assignee:
Micron Technology, Inc. - Boise ID
International Classification:
G09G 322
US Classification:
345 74
Abstract:
A current measuring circuit for a field emission display includes a testing circuit coupled between a high voltage testing source and the display. The testing circuit includes a sampling circuit formed from a sampling impedance coupled in parallel with a high isolation switch. In one embodiment, the sample circuit is on the high voltage side of the testing source. In another embodiment, the sampling circuit is on the return (low voltage) side of the testing source. In normal operation, the switch is closed to provide the testing voltage directly to the display. During testing, the switch is open so that current flows through the sampling impedance. A sensing circuit coupled to the output of the sampling impedance determines a voltage change in response to opening of the switch. In response to a sensed voltage change, a microprocessor-based controller computes the current drawn by the display. A burn-in system includes a bank of displays within a burn-in oven each selectively coupleable to the testing circuit by respective switches.
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Dwayne K Kreipl from Boise, ID, age ~56 Get Report