Eiichi Hosomi

6768206, Jul 27, 2004

May 7, 2002

10/141685

Eiichi Hosomi - Austin TX

Kabushiki Kaisha Toshiba - Tokyo

H01L 2348

257774, 257773, 257778, 257786

An exemplary embodiment of the present invention described and shown in the specification and drawings is a substrate that has lattice points and interstitial points. The substrate includes a surface, a plurality pads located on the surface at interstitial points, and a plurality of vias located in the substrate only at lattice points.

7087988, Aug 8, 2006

Jul 30, 2002

10/209498

Eiichi Hosomi - Austin TX, US

Kabushiki Kaisha Toshiba - Tokyo

H01L 23/02

257686, 257777, 257698

An exemplary embodiment of the present invention described and shown in the specification and drawings is a semiconductor packaging apparatus that includes a first substrate for coupling to an electronic component, and a second substrate for accommodating the electronic component coupled to the first substrate.

7227260, Jun 5, 2007

Oct 26, 2004

10/973735

Yuichi Goto - Austin TX, US
Eiichi Hosomi - Austin TX, US

Kabushiki Kaisha Toshiba - Tokyo

H01L 23/34
H01L 23/48
H01L 23/52
H01L 29/40

257724, 257786, 257773, 257924, 257E25015, 361782

Systems and methods for substrate layers used in attaching devices to a semiconductor package are disclosed. A novel pad structure may be employed on a substrate layer which has pads, each pad having a common electrical potential. Multiple pad openings may be employed on a single pad, allowing the attachment of multiple terminals of one or more decoupling capacitors to a single pad. These pads and pad openings can be arranged according to the type of decoupling capacitor employed, allowing a greater total pad area to be utilized in conjunction with a set of pad openings, while simultaneously allowing the multiple pad openings on the pad to be placed closer together, reducing the ESL and ESR of the path between the semiconductor and the decoupling capacitors, increasing the mechanical reliability of the semiconductor package and allowing a higher density of decoupling capacitors to be coupled to a given area.

7492570, Feb 17, 2009

Apr 13, 2005

11/105113

Eiichi Hosomi - Austin TX, US
Paul M. Harvey - Austin TX, US

Kabushiki Kaisha Toshiba - Tokyo
International Business Machines Corporation - Armonk NY

H01G 4/228

3613062, 3613061, 3613063, 3613211, 361311, 361303

Systems and methods for reducing switching noise in an integrated circuit. In one embodiment, decoupling capacitors are connected to the integrated circuit from the underside of the substrate on which the integrated circuit die is manufactured. The decoupling capacitors are positioned with a higher concentration in the “hot spot” areas of the integrated circuit instead of being evenly distributed. In one embodiment, the decoupling capacitors and the corresponding hole(s) in a circuit board on which the integrated circuit is mounted are positioned so that the circuit board provides support for the central portion of the integrated circuit and thereby prevents the integrated circuit from flexing away from the heat sink/spreader. In one embodiment, the concentration of vias connecting the different ground planes and/or power planes within the integrated circuit is higher in hot spots than in other areas.

7501698, Mar 10, 2009

Oct 26, 2004

10/973373

Eiichi Hosomi - Austin TX, US

Kabushiki Kaisha Toshiba - Tokyo

H01L 23/12

257698, 257700, 257737, 257438, 257778, 257E23003, 438106

Systems and methods for a structure for a power distribution network intended to distribute power from a PCB to a semiconductor device on a package. These improved power distribution networks may reduce current crowding in the BGA balls of a package and may serve to more equitably distribute current through the BGA balls of the package through increasing the impedance of the package or decreasing the impedance of the PCB to which the package is coupled. These systems and methods may increase the impedance of the package through various arrangements of the coupling between BGA balls and planes of the package. By the same token, these systems and methods may decrease the impedance of the PCB coupled to the package by arrangement of the coupling between the PCB and the BGA balls of the package.

7531751, May 12, 2009

Apr 26, 2005

11/114362

Eiichi Hosomi - Austin TX, US
Yuichi Goto - Austin TX, US

Kabushiki Kaisha Toshiba - Tokyo

H05K 1/00

174250, 174255, 333 33

Systems and methods for a structure for a package substrate for use in a semiconductor package are disclosed. Package substrates formed according to the systems and methods of the present invention may exhibit improved signal integrity and quality. In order to achieve this increase signal integrity, these systems and methods may endeavor to obtain equalization, or matching, of impedances in signal traces in or on the package substrate by removing material from one or more layers of a package substrate in a region of high signal density. Removing material from these layers may serve to increase the impedance of a signal trace within a region of high signal density such that the impedance of the signal trace with the region of high signal density is substantially matched to the impedance of the signal trace outside the region of high-signal density.

7817439, Oct 19, 2010

Jun 26, 2006

11/474811

Eiichi Hosomi - Austin TX, US

Kabushiki Kaisha Toshiba - Tokyo

H05K 1/18

361763, 361764, 361784

Systems, methods and apparatuses for low noise power distribution networks for use with semiconductor devices are disclosed. Embodiments of these systems and methods provide a power distribution network comprising a set of individual power distribution networks, each of the individual power distribution networks operable to provide power to a corresponding functional block of the semiconductor device. These individual power distribution networks may be coupled through capacitors between the power supplies or grounds of each individual power distribution network, such that the individual power distribution networks are coupled in a manner operable to pass AC current between them.

20060237829, Oct 26, 2006

Apr 26, 2005

11/114808

Eiichi Hosomi - Austin TX, US

H01L 23/02

257678000

Systems and methods for a structure for semiconductor packages where the effects that features on the package substrate have on the impedance of signal traces within the semiconductor package is substantially reduced. These systems and methods may allow a feature, or multiple features, to be placed anywhere on the semiconductor package while still minimizing the effect of these features on the impedance of signal traces within the package substrate of the semiconductor package that are beneath these features. In particular, these systems and methods may be useful in a semiconductor package with an air vent, such that the placement of an air vent or air vents in the semiconductor package does not affect signal traces beneath the air vent. Thus, a design rule applicable to signal traces in the remainder of that region may be applied to any signal traces that happen to exist beneath the air vent.