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Stuart A Sieg

from Albany, NY
Age ~39
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Also known as:
Stuart A Seig
Phone and address:
81 Manning Blvd, Albany, NY 12203
Related to:
Yong O Wang, 62Katherine Sieg
Connected to:
Mae L Sieg, 99Nicole M Sieg, 31Priscilla V Sieg, 94Rachel E Sieg, 40Randal M Sieg, 67Reni R Sieg, 68Wanda Sieg, 94Wolfgang K Sieg, 63Bonnie E Siegal, 72Chris J Siegal, 50

Stuart Sieg Phones & Addresses

  • 81 Manning Blvd, Albany, NY 12203
  • Hopewell Junction, NY
  • Beacon, NY
  • Hillsboro, NH
  • Rochester, NY

Resumes

Resumes

Stuart Sieg Photo 1

Manager Interconnect Patterning Research

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Location:
Albany, NY
Industry:
Research
Work:
Ibm
Manager Interconnect Patterning Research
Education:
Rochester Institute of Technology 2003 - 2008
Bachelors, Bachelor of Science, Engineering
Skills:
Design of Experiments
Semiconductors
Lithography
Thin Films
Cmos
Characterization
Process Engineering
Testing
Simulations
Stuart Sieg Photo 2

Stuart Sieg

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Publications

Us Patents

Sem Repair For Sub-Optimal Features

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US Patent:
8450120, May 28, 2013
Filed:
Mar 30, 2012
Appl. No.:
13/435308
Inventors:
Stuart A. Sieg - Hopewell Junction NY, US
Kourosh Nafisi - Hopewell Junction NY, US
Eric Peter Solecky - Hopewell Junction NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/00
US Classification:
438 4, 438 14, 700110
Abstract:
A method and system for repairing photomasks is disclosed. A scanning electron microscope (SEM) is used to identify, measure, and correct defects. The SEM is operated in multiple modes, including a measuring mode and a repair mode. The repair mode is of higher landing energy and exposure time than the measuring mode, and induces shrinkage in the photoresist to correct various features, such as vias that are too small.

Sem Repair For Sub-Optimal Features

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US Patent:
20120190134, Jul 26, 2012
Filed:
Jan 26, 2011
Appl. No.:
13/013947
Inventors:
Stuart A. Sieg - Hopewell Junction NY, US
Kourosh Nafisi - Hopewell Junction NY, US
Eric Peter Solecky - Hopewell Junction NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 21/66
B23Q 15/00
G06F 17/30
US Classification:
438 4, 707769, 29705, 707E17014, 257E21525
Abstract:
A method and system for repairing photomasks is disclosed. A scanning electron microscope (SEM) is used to identify, measure, and correct defects. The SEM is operated in multiple modes, including a measuring mode and a repair mode. The repair mode is of higher landing energy and exposure time than the measuring mode, and induces shrinkage in the photoresist to correct various features, such as vias that are too small.

Backside Power Rails

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US Patent:
20230100113, Mar 30, 2023
Filed:
Sep 29, 2021
Appl. No.:
17/488389
Inventors:
- Armonk NY, US
Stuart Sieg - Albany NY, US
Somnath Ghosh - Clifton Park NY, US
Kisik Choi - Watervliet NY, US
Rishikesh Krishnan - Cohoes NY, US
Alexander Reznicek - Troy NY, US
International Classification:
H01L 23/528
H01L 23/522
H01L 21/768
H01L 21/311
Abstract:
Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.

Selective Source/Drain Recess For Improved Performance, Isolation, And Scaling

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US Patent:
20200411682, Dec 31, 2020
Filed:
Jun 27, 2019
Appl. No.:
16/454561
Inventors:
- Armonk NY, US
Brent Anderson - Jericho VT, US
JUNLI WANG - Slingerlands NY, US
Stuart Sieg - Albany NY, US
Christopher J. Waskiewicz - Rexford NY, US
International Classification:
H01L 29/78
H01L 29/66
H01L 21/8234
Abstract:
Embodiments of the present invention are directed to a method for increasing the available width of a shallow trench isolation region. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A source or drain is formed on a surface of the substrate between the semiconductor fin and the substrate. A liner is formed over a surface of the semiconductor fin and a surface of the substrate is recessed to expose a sidewall of the source or drain. A mask is formed over the semiconductor fin and the liner. The mask is patterned to expose a top surface and a sidewall of the liner. A sidewall of the source or drain is recessed and a shallow trench isolation region is formed on the recessed top surface of the substrate. The shallow trench isolation region is adjacent to the recessed sidewall of the source or drain.

Fin Field Effect Transistor Devices With Self-Aligned Gates

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US Patent:
20200294803, Sep 17, 2020
Filed:
Mar 14, 2019
Appl. No.:
16/353641
Inventors:
- Armonk NY, US
Stuart A. Sieg - Albany NY, US
Ruilong Xie - Niskayuna NY, US
John R. Sporre - Albany NY, US
International Classification:
H01L 21/28
H01L 29/66
H01L 21/3213
H01L 29/49
H01L 29/78
Abstract:
A method of forming adjacent fin field effect transistor devices is provided. The method includes forming at least two vertical fins in a column on a substrate, depositing a gate dielectric layer on the vertical fins, and depositing a work function material layer on the gate dielectric layer. The method further includes depositing a protective liner on the work function material layer, and forming a fill layer on the protective liner. The method further includes removing a portion of the fill layer to form an opening between an adjacent pair of two vertical fins, where the opening exposes a portion of the protective liner. The method further includes depositing an etch-stop layer on the exposed surfaces of the fill layer and protective liner, forming a gauge layer in the opening to a predetermined height, and removing the exposed portion of the etch-stop layer to form an etch-stop segment.

Semiconductor Fin Length Variability Control

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US Patent:
20200144069, May 7, 2020
Filed:
Jan 8, 2020
Appl. No.:
16/737737
Inventors:
- Armonk NY, US
Ekmini A. De Silva - Slingerlands NY, US
Stuart A. Sieg - Albany NY, US
Eric Miller - Watervliet NY, US
International Classification:
H01L 21/308
H01L 21/8234
H01L 29/78
H01L 29/66
Abstract:
Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.

Approach To Prevent Collapse Of High Aspect Ratio Fin Structures For Vertical Transport Fin Field Effect Transistor Devices

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US Patent:
20200098639, Mar 26, 2020
Filed:
Sep 24, 2018
Appl. No.:
16/139932
Inventors:
- Armonk NY, US
Stuart A. Sieg - Albany NY, US
Praveen Joseph - Albany NY, US
Ekmini A. De Silva - Slingerlands NY, US
International Classification:
H01L 21/8234
H01L 21/308
H01L 21/3105
H01L 21/02
H01L 21/311
Abstract:
A method of preventing the collapse of fin structures is provided. The method includes forming a plurality of vertical fins on a substrate, and a hard mask stack on each of the vertical fins. The method further includes forming a cover layer on the plurality of vertical fins and hard mask stacks, and reducing the height of the cover layer to expose an upper portion of each of the hard mask stacks. The method further includes forming a bracing layer on the reduced height cover layer and exposed portion of each of the hard mask stacks, and removing a portion of the bracing layer to expose a portion of the reduced height cover layer and form a bracing segment on the exposed portion of each of the hard mask stacks. The method further includes removing the reduced height cover layer.

Controlling Gate Length Of Vertical Transistors

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US Patent:
20200075761, Mar 5, 2020
Filed:
Aug 28, 2018
Appl. No.:
16/114613
Inventors:
- Armonk NY, US
Indira Seshadri - Niskayuna NY, US
Ekmini A. De Silva - Slingerlands NY, US
Stuart A. Sieg - Albany NY, US
International Classification:
H01L 29/78
H01L 29/66
H01L 21/768
H01L 21/8234
H01L 21/033
H01L 21/02
H01L 29/08
Abstract:
A semiconductor device includes a semiconductor fin that extends from a first source/drain to an opposing second source/drain. The semiconductor fin includes a channel region between the first and second source/drains. The semiconductor device further includes a spacer having an upper surface having the second source/drain formed thereon, and a gate structure a gate structure wrapping around the channel region. The gate structure includes a tapered portion that contacts the spacer.
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Stuart A Sieg from Albany, NY, age ~39 Get Report