Christopher M Hale from Boise, ID, age 41

Professional Records

Lawyers & Attorneys

Christopher David Hale - Lawyer

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Licenses:

New York - Currently registered 2006

Education:

Columbia University School of Law

Christopher Hale - Lawyer

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Office:

Sidley Austin LLP

Specialties:

Corporate & Incorporation
Securities & Investment Fraud
Mergers & Acquisitions

ISLN:

920539475

Admitted:

2008

University:

University of Notre Dame, B.B.A., 2005

Law School:

Northwestern University School of Law, J.D., 2008

Christopher Hale - Lawyer

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Specialties:

Government Contracts
Investigations & International Trade
False Claims Act
Litigation
Aerospace and Defense
Regulated Industries

ISLN:

918090247

Admitted:

2004

University:

Cornell University, B.S., 2001

Law School:

Stanford University, J.D., 2004; Stanford University, J.D., 2004

Medicine Doctors

Christopher Gordon Hale

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Specialties:

Emergency Medicine

Education:

Oregon Health & Science University (2009)

Christopher Stephen Hale

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Resumes

Senior Project Manager

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Location:

66 Glen Eden Ave, Oakland, CA 94611

Industry:

Construction

Work:

Mccarthy Building Companies, Inc.
Senior Project Manager
Mccarthy Building Companies, Inc. Jan 2015 - Dec 2016
Program Manager
Mccarthy Building Companies, Inc. Mar 2013 - Dec 2013
Project Manager
Mccarthy Building Companies, Inc. Jan 2012 - Feb 2013
Cost and Contract Manager
Mccarthy Building Companies, Inc. Sep 2008 - Jan 2012
Assistant Project Manager

Education:

Boise State University 2003 - 2005
Bachelors, Bachelor of Science, Engineering, Construction University of Washington 1999 - 2001
Bachelors, Bachelor of Arts, Management

Skills:

Change Orders
Pre Construction
Construction Management
Value Engineering
Contract Management
Constructability
Subcontracting
Project Estimation
Leed Ap
Cpm Scheduling
Submittals
Procurement
Project Management
Primavera P6
Design Build
Project Planning
Suretrack
Rfi
Process Scheduler
Project Coordination
Building Information Modeling
Cost Management
Bim
Leadership
Leadership In Energy and Environmental Design
Oshpd
Multiple Project Coordination
Lean Management
Lean Construction
Meeting Facilitation
Primavera
Program Management
Process Improvement
Design Management
Program
Integrated Project Delivery
Field Coordination

Painter

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Work:

Painter

Regional Sales Manager

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Work:

Regional Sales Manager

Christopher Hale

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Industry:

Hospital & Health Care

Christopher Hale

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Christopher Hale

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Christopher Hale

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Ceo Of Tricen Technologies

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Position:

CEO at Tricen Technologies, Co-Founder at Deadstick Enterprises

Location:

Port Saint Lucie, Florida

Industry:

Oil & Energy

Work:

Tricen Technologies since Sep 2009
CEO
Deadstick Enterprises - Port Saint Lucie, FL since Jan 2012
Co-Founder
Wexxle - Port Saint Lucie, FL Nov 2003 - Jan 2012
Founder
[UNLISTED COMPANY] Aug 1997 - Jan 2010
Outage Services Division Manager

Education:

University of Phoenix 2007 - 2009
BS, Business

Skills:

Ultrasonics
Eddy Current
NDT
Quality Assurance
Instructing
Executive Management
Web Development
Web Application Design
Database Development
Network Engineering
Systems Engineering
Marketing Strategy
Digital Marketing
Inspection
Oil/Gas
Nuclear Energy
Aerospace
Nondestructive Testing
Certified Project Manager
Nuclear
Databases

Interests:

My family, being an entrepreneur, surfing, golfing, technology.

Certifications:

ET Level III, ASNT
MT Level III, ASNT
PT Level III, ASNT
UT Level III, CP-189
Qualified Data Analyst (QDA), EPRI
Certified Instructor, Microsoft

Business Records

Name / Title

Company / Classification

Phones & Addresses

Christopher Hale
Managing

The Duke Boys LLC

Christopher J Hale

HALE BROTHERS LLC

Christopher Hale

NEW BEGINNINGS EMPOWERMENT CENTER

Christopher L. Hale

PRITECH, INC

Christopher G Hale
Unknown Historic

A. E., INC

Christopher T Hale
President

CTH HOMES, INC

3907 India Cv, Gulf Breeze, FL 32561
7504 Progress Dr, Amarillo, TX 79119

Publications

Us Patents

Memory Device With Dynamic Cache Management

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US Patent:

20210342261, Nov 4, 2021

Filed:

Jul 13, 2021

Appl. No.:

17/374906

Inventors:

- Boise ID, US
Peter Feeley - Boise ID, US
Ashutosh Malshe - Fremont CA, US
Daniel J. Hubbard - Boise ID, US
Christopher S. Hale - Boise ID, US
Kevin R. Brandt - Boise ID, US
Sampath K. Ratnam - Boise ID, US
Yun Li - Fremont CA, US
Marc S. Hamilton - Eagle ID, US

International Classification:

G06F 12/02
G06F 12/0891
G06F 3/06
G06F 12/06
G06F 12/00

Abstract:

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Periodic Flush In Memory Component That Is Using Greedy Garbage Collection

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US Patent:

20210342262, Nov 4, 2021

Filed:

Jul 14, 2021

Appl. No.:

17/375478

Inventors:

- Boise ID, US
Peter Sean Feeley - Boise ID, US
Sampath K. Ratnam - BOISE ID, US
Ashutosh Malshe - Fremont CA, US
Christopher S. Hale - Boise ID, US

International Classification:

G06F 12/02
G06F 12/0897
G06F 12/128

Abstract:

A method includes identifying a first block of a plurality of blocks stored at a first memory based on an amount of valid data of the first block, and writing the valid data of the first block from the first memory to a second memory. The first memory has a first memory type and the second memory has a second memory type different from the first memory type. The method further includes identifying a second block of the plurality of blocks stored at the first memory based on an age of valid data of the second block, determining that the age of the valid data of the second block satisfies a threshold condition, and in response to determining that the age of the valid data of the second block satisfies the threshold condition, writing the valid data of the second block from the first memory to the second memory.

Managing Block Retirement For Temporary Operational Conditions

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US Patent:

20210118519, Apr 22, 2021

Filed:

Oct 22, 2019

Appl. No.:

16/660483

Inventors:

- Boise ID, US
Sampath K. Ratnam - Boise ID, US
Scott A. Stoller - Boise ID, US
Preston A. Thomson - Boise ID, US
Kevin R. Brandt - Boise ID, US
Marc S. Hamilton - Eagle City ID, US
Christopher S. Hale - Boise ID, US

International Classification:

G11C 29/38
G11C 29/44

Abstract:

A processing device in a memory system detects a data loss occurrence in a block of a memory component. The processing device identifies a behavioral criterion associated with the data loss occurrence in the block of the memory component. The processing device further increments a counter associated with the block in response to an occurrence of the behavioral criterion, wherein a value of the counter corresponds to a number of occurrences of a plurality of behavioral criteria associated with data loss occurrences in the block. Responsive to determining that the value of the counter satisfies a first threshold criterion, the processing device designates the block as a quarantined block, performs a stress test of a plurality of stress tests of the block, and responsive to the block failing a first stress test, the processing device retires the block of the memory component.

Memory Device With Dynamic Cache Management

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US Patent:

20200097402, Mar 26, 2020

Filed:

Nov 27, 2019

Appl. No.:

16/697724

Inventors:

International Classification:

G06F 12/02
G06F 12/0891
G06F 3/06
G06F 12/06
G06F 12/00

Abstract:

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, and designate a storage mode for an available memory block based on the valid data, wherein the storage mode is for configuring memory cells in the available memory block as cache memory that stores a number of bits less than maximum storage capacities thereof for subsequent or upcoming data writes.

Memory Devices And Electronic Systems Having A Hybrid Cache Including Static And Dynamic Caches, And Related Methods

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US Patent:

20190250824, Aug 15, 2019

Filed:

Apr 26, 2019

Appl. No.:

16/396432

Inventors:

- Boise ID, US
Ashutosh Malshe - Fremont CA, US
Sampath K. Ratnam - Boise ID, US
Peter Feeley - Boise ID, US
Michael G. Miller - Boise ID, US
Christopher S. Hale - Boise ID, US
Renato C. Padilla - Boise ID, US

International Classification:

G06F 3/06
G06F 12/0888
G06F 12/0893
G06F 12/02
G06F 11/34

Abstract:

Memory devices are disclosed. A memory device may include main memory and a hybrid cache. The hybrid cache includes a dynamic cache including x-level cell (XLC) blocks of non-volatile memory cells shared between the dynamic cache and the main memory. The hybrid cache further includes a static cache including single-level cell (SLC) blocks of non-volatile memory cells. The memory device further includes a memory controller configured to disable at least one of the static cache and the dynamic cache responsive to a workload of the hybrid cache relative to a Total Bytes Written (TBW) Spec for the memory device. Methods of operating a memory device and an electronic system are also described.

Memory Device With Dynamic Storage Mode Control

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US Patent:

20190065365, Feb 28, 2019

Filed:

Aug 31, 2017

Appl. No.:

15/693153

Inventors:

- Boise ID, US
Kishore Kumar Muchherla - Fremont CA, US
Peter Feeley - Boise ID, US
Ashutosh Malshe - Fremont CA, US
Daniel J. Hubbard - Boise ID, US
Christopher S. Hale - Boise ID, US
Kevin R. Brandt - Boise ID, US
Sampath K. Ratnam - Boise ID, US

International Classification:

G06F 12/02
G06F 12/0891

Abstract:

A memory system includes: a memory array including a plurality of memory cells, the plurality of memory cells including a plurality of cache memory cells; and a controller coupled to the memory array, the controller configured to: track usage of a first subset of the plurality of cache memory cells operating in a single-level cell (SLC) mode, wherein the tracking includes monitoring for an idle time event; and designate a storage mode for a second subset of the plurality of cache memory cells based on the tracked usage of the first subset, wherein the storage mode determines a storage density to be used for data writes.

Memory Device With Dynamic Cache Management

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US Patent:

20190065366, Feb 28, 2019

Filed:

Aug 31, 2017

Appl. No.:

15/693178

Inventors:

International Classification:

G06F 12/02
G06F 12/0891
G11C 11/56

Abstract:

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and designate a storage mode for an available memory block based on the valid data measure, wherein the storage mode is for controlling a number of bits stored per each of the memory cells for subsequent or upcoming data writes.

Memory Device With Dynamic Storage Mode Control

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US Patent:

20190065367, Feb 28, 2019

Filed:

Oct 22, 2018

Appl. No.:

16/167345

Inventors:

International Classification:

G06F 12/02
G06F 12/0891

Abstract:

Wikipedia

Christopher Hale (writer)

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Christopher Hale is a British writer and documentary producer. He was educated at the University of Sussex and Slade School of Fine Art - and began his ...