Danielle L Thomas

6440814, Aug 27, 2002

Dec 30, 1998

09/223629

Arnaud Yves Lepert - Lafayette CA
Danielle A. Thomas - Dallas TX

STMicroelectronics, Inc. - Carrollton TX

H01L 2120

438393, 369126

A structure and method is disclosed for dissipating electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive layer and passivation layers disposed over the underlying dielectric layer wherein the conductive layer diffuses electrostatic charges at the surface of the integrated circuit.

6478976, Nov 12, 2002

Dec 30, 1998

09/224815

Arnaud Yves Lepert - Lafayette CA
Danielle A. Thomas - Dallas TX

STMicroelectronics, Inc. - Carrollton TX

H01L 2100

216 18, 216 13, 216 17, 216 79, 438720

A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

6555888, Apr 29, 2003

Jul 1, 2002

10/186801

Arnaud Yves Lepert - Lafayette CA
Danielle A. Thomas - Dallas TX

STMicroelectronics, Inc. - Carrollton TX

H01L 2982

257415, 341 33, 382124, 3612831

A structure and method is disclosed for dissipating electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive layer and passivation layers disposed over the underlying dielectric layer wherein the conductive layer diffuses electrostatic charges at the surface of the integrated circuit.

6740945, May 25, 2004

Jun 20, 2002

10/175700

Arnaud Yves Lepert - Lafayette CA
Danielle A. Thomas - Dallas TX

STMicroelectronics, Inc. - Carrollton TX

H01L 2714

257414, 257108, 257415, 257418, 257419, 382124

A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

6746953, Jun 8, 2004

Aug 9, 2001

09/925765

Alan H. Kramer - Berkeley CA
Danielle A. Thomas - Dallas TX

STMicroelectronics, Inc. - Carrollton TX

H01L 214763

438637

Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different dice after separation of the dice along the boundary.

63006707, Oct 9, 2001

Jul 26, 1999

9/360836

Alan H. Kramer - Berkeley CA
Danielle A. Thomas - Dallas TX

STMicroelectronics, Inc. - Carrollton TX

H01L 2940

257621

Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different dice after separation of the dice along the boundary.

63301458, Dec 11, 2001

Dec 30, 1998

9/223346

Arnaud Yves Lepert - Lafayette CA
Danielle A. Thomas - Dallas TX

STMicroelectronics, Inc. - Carrollton TX

G06K 928

361220

A structure and method is disclosed for grounding an electrostatic discharge device of an integrated circuit to dissipate electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry and a conductive layer disposed over the underlying dielectric layer, wherein the conductive layer diffuses electrostatic charges at the surface of the integrated circuit to ground. The conductive material not only dissipates electrostatic charges to the ground, but may also protect at least a portion of the edge of the sensor chip from mechanical stress.