David E Daniel

6354908, Mar 12, 2002

Jan 4, 2001

09/754429

Derryl D. J. Allman - Colorado Springs CO
David W. Daniel - Divide CO
John W. Gregory - Colorado Springs CO

LSI Logic Corp. - Milpitas CA

B24B 4900

451 6, 451 41

A method of planarizing a first side of a semiconductor wafer with a polishing system includes the step of polishing the first side of the wafer in order to remove material from the wafer. The method also includes the step of moving a lens of a confocal optical system between a number of lens positions so as to maintain focus on the first side of the wafer during the polishing step. The method further includes the step of determining a rate-of-movement value based on movement of the lens during the moving step. Moreover, the method includes the step of stopping the polishing step if the rate-of-movement value has a predetermined relationship with a movement threshold value. An apparatus for polishing a first side of a semiconductor wafer is also disclosed.

6372520, Apr 16, 2002

Jul 10, 1998

09/113594

George H. Maggard - Colorado Springs CO
David W. Daniel - Divide CO

LSI Logic Corporation - Milpitas CA

H01L 2100

438 4, 438308, 438378, 438795

A method and apparatus for repairing and improving the endurance characteristics of process damaged oxide film formed in a semiconductor device involving sonic annealing by vibrating or oscillating a wafer at a predetermined frequency, wave amplitude, and duration. A signal from a frequency generator is amplified by a voltage amplifier and then sent to a speaker or other acoustic device for the production of vibrating acoustical wave energy. This acoustical wave energy is then directed at a submicron device wafer during a specified time period in order to anneal the gate oxide and, thereby, improve the characteristics of the oxide film.

6925924, Aug 9, 2005

Oct 14, 2003

10/684858

Ernest L. Baker - Wantage NJ, US
David C. Daniel - Missouri City TX, US
David S. Wesson - Ft. Worth TX, US
Arthur S. Daniels - Rockaway NJ, US
Robert E. Davis - Joshua TX, US

Molycorp Inc. - Mountain Pass CA

E21B043/116

87 1151

A non-linear shaped charge perforator for use in perforating an oil and gas formation into which a wellbore has been drilled comprises a monolithic, axisymmetric metal case in which is disposed a main explosive charge between the front of the case, which is closed with a concave metal liner, and the closed back end of the case. The main explosive charge contains multiple initiation points, preferably two initiation points located about 180 apart on the outside surface of the charge, so that when the perforator is detonated the main charge is initiated such that the metal liner is collapsed into a non-circular jet, preferably a fan-shaped jet, that pierces the casing of the wellbore and forms non-circular perforations, preferably slot-shaped perforations, in the surrounding formation.

20050188878, Sep 1, 2005

Mar 7, 2005

11/073235

Ernest Baker - Wantage NJ, US
David Daniel - Missouri City TX, US
David Wesson - Ft. Worth TX, US
John Burba - Boulder City NV, US
Arthur Daniels - Rockaway NJ, US
Robert Davis - Joshua TX, US

F42B012/20

102306000, 102476000

A non-linear shaped charge perforator for use in perforating an oil and gas formation into which a wellbore has been drilled comprises a monolithic, axisymmetric metal case in which is disposed a main explosive charge between the front of the case, which is closed with a concave metal liner, and the closed back end of the case. The main explosive charge contains multiple initiation points, preferably two initiation points located about 180 apart on the outside surface of the charge, so that when the perforator is detonated the main charge is initiated such that the metal liner is collapsed into a non-circular jet, preferably a fan-shaped jet, that pierces the casing of the wellbore and forms non-circular perforations, preferably slot-shaped perforations, in the surrounding formation.

60966254, Aug 1, 2000

Oct 20, 1997

8/954006

David W. Daniel - Divide CO
Theodore C. Moore - Woodland Park CO
Crystal J. Hass - Colorado Springs CO

LSI Logic Corporation - Milpitas CA

H01L 21322

438473

The present invention provides a method for manufacturing a semiconductor device on a substrate. The process involves denuding the substrate by heating to create a denuded zone within the substrate. A screen oxide layer is formed prior to implanting ions into the substrate. This oxide layer remains during the implantation step. The screen oxide layer is removed when forming gates for the semiconductor device.

59665998, Oct 12, 1999

May 21, 1996

8/651018

John D. Walker - Colorado Springs CO
David W. Daniel - Divide CO

LSI Logic Corporation - Milpitas CA

H01L 218238

438228

A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants.

60777834, Jun 20, 2000

Jun 30, 1998

9/109335

Derryl D. J. Allman - Colorado Springs CO
David W. Daniel - Divide CO
Michael F. Chisholm - Garland TX

LSI Logic Corporation - Milpitas CA

H01L 21302

438691

A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes heating a back surface of the semiconductor wafer to a first temperature level so as to cause a front surface of the semiconductor wafer to have a second temperature level. Another step of the method includes polishing the semiconductor wafer whereby material of the first layer is removed from the semiconductor wafer. The polishing step causes the second temperature level of the front surface to change at a first rate as the material of the first layer is being removed. The method also includes the step of halting the polishing step in response to the second temperature level of the front surface changing at a second rate that is indicative of the second layer being polished during the polishing step. Polishing systems are also disclosed which detect a polishing endpoint for a semiconductor wafer based upon heat conducted through the semiconductor wafer.

62355902, May 22, 2001

Dec 18, 1998

9/216394

David W. Daniel - Divide CO
Dianne G. Pinello - Woodland Park CO
Michael F. Chisholm - Garland TX

LSI Logic Corporation - Milpitas CA

H01L 218234

438275

Techniques for fabricating integrated circuits having devices with gate oxides having different thicknesses and a high nitrogen content include forming the gate oxides at pressures at least as high as 2. 0 atmospheres in an ambient of a nitrogen-containing gas. In one implementation, a substrate includes a first region for forming a first device having a gate oxide of a first thickness and a second region for forming a second device having a gate oxide of a second different thickness. A first oxynitride layer is formed on the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres. A portion of the first oxynitride layer is removed to expose a surface of the substrate on the second region. Subsequently, a second oxynitride is formed over the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres to form the first and second gate oxides. Respective gate electrodes are formed over the first and second gate oxides.