David N Rice

7564665, Jul 21, 2009

Jan 10, 2007

11/621724

Patrick J. Holly - Tempe AZ, US
David Rodriguez - Phoenix AZ, US
David R. Rice - Phoenix AZ, US

Standard Microsystems Corporation - Hauppauge NY

H02H 9/00

361 56

A system, e. g. an integrated circuit or part, may include a plurality of pads, e. g. digital I/O pads, each comprising a physical pad and associated pad circuit. In case of an ESD event affecting one or more of the digital I/O pads, PMOS devices configured in an output buffer section between an I/O pad supply rail and the physical output pad—within their respective pad circuits in the affected digital I/O pads—may all be turned on in response to the ESD event. This may allow the capacitance of each pad, in some cases approximately 3 pF capacitance per pad, to charge up, absorbing the energy of the ESD event and reducing the peak voltage the integrated circuit or part experiences as a result of the ESD event. The reduced peak voltage may be directly correlated with improved ESD performance of the product.

7742265, Jun 22, 2010

Jun 6, 2005

11/145903

David R. Rice - Phoenix AZ, US

Standard Microsystems Corporation - Hauppauge NY

H02H 9/00

361 56

In one embodiment, an ESD protection circuit comprises a switchable current sinking circuit connected to a positive ESD clamp rail voltage, which may be a power supply voltage, and a single trigger control circuit coupled to a control connection of the switchable current sinking circuit. The single trigger control circuit may be configured to couple the control connection of the switchable current sinking circuit to a negative ESD clamp rail voltage, which may be signal ground, during an ESD event occurring on the positive ESD clamp rail connection. In one embodiment, the switchable current sinking circuit is capable of sinking large amounts of current, and the ESD protection circuit is tolerant of rail voltages that exceed the breakdown voltage of semiconductor devices used in constructing the ESD circuit. In one embodiment, the single trigger control circuit is implemented with a single n-well, thereby minimizing the amount of required silicon area during fabrication of the ESD protection circuit.

60313366, Feb 29, 2000

Jun 17, 1998

9/098769

Robert C. Rumbaugh - Scottsdale AZ
Robert T. Smith - Tempe AZ
Johann Trujillo - Mesa AZ
Chenggang Xie - Phoenix AZ
Scott V. Johnson - Scottsdale AZ
Curtis D. Moyer - Phoenix AZ
David M. Rice - Chandler AZ

Motorola, Inc. - Schaumburg IL

G09G 310

3151693

A field emission display (100) includes a cathode plate (110) having a plurality of electron emitters (114), an anode plate (122) having an anode (124) connected to a potential source (126), and an anode voltage pull-down circuit (127) having an input (106) and an output (104). Output (104) is connected to anode (124), and input (106) is connected to potential source (126). Preferably, anode voltage pull-down circuit (127) causes an anode voltage (120) at anode (124) to drop to about ground potential prior to generation of a discharge current by electron emitters (114) for neutralizing positively electrostatically charged surfaces (137, 138) within field emission display (100).