De Manh Nguyen

6446164, Sep 3, 2002

Mar 14, 1997

08/818060

De H. Nguyen - Milpitas CA
Raymond M. Chu - Saratoga CA

Integrated Device Technology, Inc. - Santa Clara CA

G06F 1200

711118, 711123, 711125, 711126, 714 30

A circuit and method for reading and writing to a microprocessors internal cache memory during a test mode of operation. During write accesses, an external data bus transmits to an internal data bus an address, cache tags and data in accordance with an external clock. During read accesses, the external data bus transmits an address and receives from the internal data bus data and cache tags. In one embodiment, during a write access, the external data bus is time-multiplexed to transmit an address, cache tags and data in two clock periods of the external clock the external data bus is time-multiplexed to transmit to the internal data bus an address in the first clock period of the external clock signal and to receive tag and data in the next successive clock periods of the external clock signal. In this embodiment, reserved pins are used to specify a cache access mode, including a test mode of operation. During the test mode, read and write buffers for the internal cache are deselected from the interal bus and the central processing unit of the microprocessor is stalled.

55640524, Oct 8, 1996

Sep 7, 1994

8/303272

De H. Nguyen - Milpitas CA
Raymond M. Chu - Saratoga CA

Integrated Device Technology, Inc. - Santa Clara CA

G06F 132

395800

A method and structure for logically disconnecting an on-chip virtual-to-physical address translation unit from a microprocessor by holding the dynamic circuits of the translation unit in precharged state. In one embodiment, the method and structure provide a fixed remapping for the virtual address. A powering down of the translation unit effects power savings when the translation unit is not required.