Douglas Gerald Martin

48478172, Jul 11, 1989

Dec 31, 1987

7/140189

Whitlow W. L. Au - Kailua HI
Douglas W. Martin - San Diego CA

The United States of America as represented by the Secretary of the Navy - Washington DC

H04B 106

367135

Target discrimination involves processing of sonar echoes in the time-dom and using features of the targets that the human auditory system uses (time separation and amplitude of echo highlights). Known targets are placed in the water and ensonified by multiple broadband transient signals. Echoes from each of the known targets have time-domain feature data extracted and stored to construct a library of known target features. Unknown targets echoes of transmitted multiple broadband transient signals are received and time-domain feature data is extracted from these. A comparison of the unknown target echo features with the known target echo features provides a discrimination of the unknown target echoes.

57480281, May 5, 1998

Oct 31, 1996

8/741731

Douglas Ele Martin - Round Rock TX

International Business Machines Corporation - Armonk NY

H03K 1704

327374

The invention is embodied in a receiver and a method for responding to an input signal. The input signal is received in a first stage of the receiver, which generates a first stage output signal responsive thereto. If the input signal does not exceed a first level, the first stage output signal is generated by an overvoltage element. That is, for this case, the overvoltage element passes the input signal through to the first stage output, and the first stage output voltage is not increased by a first stage pullup element. If, on the other hand, the input signal exceeds the first level, the first stage output signal voltage level is increased by the first stage pullup element to a higher output voltage level. The output signal from the first stage is received in a second stage. The second stage generates a second stage output responsive thereto.

58182802, Oct 6, 1998

Dec 11, 1995

8/570042

Douglas Ele Martin - Round Rock TX

International Business Machines Corporation - Armonk NY

H03K 1704

327374

A shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to switches in logic state of the input signal and whose voltage level is shifted with respect to the input signal. A feedback circuit feeds a signal derived from the output signal back to the shifter to precondition the shifter so that the speed of the output signal switching is accelerated.

60844329, Jul 4, 2000

Mar 30, 1998

9/050162

Daniel Mark Dreps - Georgetown TX
Douglas Ele Martin - Round Rock TX

International Business Machines Corporation - Armonk NY

H03K 1716
H03K 19175

326 83

A driver circuit has an output node coupled to a chip pad. A first PFET and a first resistor are connected between a power supply and the output node, wherein the first resistor is connected between the first PFET and the output node. A first NFET and a second resistor are connected between a ground potential and the output node, wherein the second resistor is connected between the first NFET and the output node. A third resistor is connected between an input to the driver circuit and a gate electrode of the first PFET. A fourth resistor is connected between the input to the driver circuit and a gate electrode of the first NFET. The pre-drive circuitry for driving the input to the PFET may include an NFET coupled between the ground potential and the input, wherein the gate electrode of the NFET receives the data signal to be driven. The NFET pre-drive circuitry may include a PFET coupled between the power supply and the input to the NFET portion of the driver circuit, wherein the gate electrode of this PFET also receives the data signal to be driven. A plurality of these driver circuits may be connected in parallel and in series in order to modify the output impedance.

47409169, Apr 26, 1988

Dec 19, 1985

6/810622

Douglas E. Martin - Round Rock TX

International Business Machines Corporation - Armonk NY

G06F 1202
G06F 1340

364900

A memory system for providing a contiguous address space and including several memory modules each having circuitry to provide information of their respective memory module capacity to a control circuit. The control circuit allocates a start address to the first memory module and allocates start addresses to the remaining memory modules in accordance with previously allocated start addresses and the memory capacities of the memories that have received their respected start addresses. In one embodiment, the control circuit includes a series of adders each connected to a memory module to receive memory capacity data. The adders are connected in series to compute the start addresses in a daisy chain fashion.

57397007, Apr 14, 1998

Sep 9, 1996

8/709706

Douglas Ele Martin - Round Rock TX

International Business Machines Corporation - Armonk NY

H03K 190185

326 80

A method and apparatus is disclosed for outputting a signal responsive to, and shifted in signal level relative to, an input signal level. A driver includes first circuitry outputting a first signal responsive to an input signal, and second circuitry outputting a second signal responsive to the input signal. The first circuitry includes circuitry for substantially shifting the first signal level relative to the input signal and responds more slowly than the second circuitry. The driver output is responsive to both the first and second signals so that the second circuitry improves driver response.

62089072, Mar 27, 2001

Jan 30, 1998

9/016653

Christopher McCall Durham - Austin TX
Visweswara Rao Kodali - Austin TX
Douglas Ele Martin - Round Rock TX
Harsh Dev Sharma - Austin TX

International Business Machines Corporation - Armonk NY

G06F19/00;17/10;7/60
7
H01L21/82

700121

A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.

57173559, Feb 10, 1998

Dec 11, 1995

8/570043

Douglas Ele Martin - Round Rock TX

International Business Machines Corporation - Armonk NY

H03K 1704

327374

In a method and apparatus for shifting the level of a signal a shifter receives a multi-logic state input signal and generates a multi-logic state output signal responsive to changes in logic state of input signal and whose voltage level is shifted with respect to the input signal. The logic low state of the output signal is shifted to a certain voltage level above ground. A first switching device sets the voltage level of the logic low state. A feedback circuit feeds a signal derived from the output signal back to the switching device to precondition the shifter so that the speed of the output signal transition from one state to another is accelerated.