Resumes
Resumes
Jagannathan Narasimhan Phones & Addresses
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49 High Ridge Rd, Mount Kisco, NY 10549 (914) 241-0514 (914) 241-0567 (914) 864-2471
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Palm Coast, FL
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49 High Ridge Rd, Mount Kisco, NY 10549 (914) 241-0567
Education
Degree:
High school graduate or higher
Emails
j***n@bigfoot.com
Public records
Vehicle Records
Jagannathan Narasimhan
View pageAddress:
49 High Rdg Rd, Mount Kisco, NY 10549
VIN:
2T2BK1BA0AC008231
Make:
LEXUS
Model:
RX 350
Year:
2010
Business Records
Name / Title
Company / Classification
Phones & Addresses
Owner
Narasimhan Jagannathan
Medical Doctor's Office
Medical Doctor's Office
23 Baldwin Hl Rd, Millwood, NY 10546
Publications
Us Patents
Method For Propagating Switching Activity Information In Digital Combinatorial Networks
View pageUS Patent:
6611945, Aug 26, 2003
Filed:
Oct 25, 2000
Appl. No.:
09/696718
Inventors:
Jagannathan Narasimhan - Millwood NY
Amir Farrahi - Peekskill NY
Amir Farrahi - Peekskill NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 4, 716 5
Abstract:
A method is provided for computing signal and switching probabilities at an output of a logic circuit in a network having multiple logic circuits. The method for computing the signal and switching probabilities includes steps of creating a truth table for a logic circuit where the truth table has entries respectively corresponding to signals at inputs of the logic circuit, choosing in sequence one of entries each representing switching of a signal at the output of the circuit, determining whether a signal at an input corresponding to the chosen entry is at logic high, assigning an event probability representing that the signal is at logic high, and accumulating event probabilities respectively assigned to signals at inputs corresponding to the chosen entries to produce the signal probability at the output of the circuit.
Methods And Apparatus For Providing Flexible Timing-Driven Routing Trees
View pageUS Patent:
7571411, Aug 4, 2009
Filed:
Jan 12, 2006
Appl. No.:
11/330937
Inventors:
Renato Fernandes Hentschke - Porto Alegre, BR
Marcelo de Oliveira Johann - Porto Alegre, BR
Jagannathan Narasimhan - Millwood NY, US
Ricardo Augusto de Luz Reis - Porto Alegre, BR
Marcelo de Oliveira Johann - Porto Alegre, BR
Jagannathan Narasimhan - Millwood NY, US
Ricardo Augusto de Luz Reis - Porto Alegre, BR
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 12, 716 13
Abstract:
A method of producing a flexible timing-driven routing tree is provided. Two or more target nodes are sorted in accordance with data criticality. A source-sink grid is built from one or more source nodes and the two or more target nodes. An initial routing tree is built comprising the one or more source nodes. A routing tree generation algorithm is executed on the initial routing tree, utilizing the sorted two or more target nodes and the source-sink grid in accordance with a user-defined timing factor to construct a flexible timing-driven routing tree. The user-defined timing factor specifies an extent of isolation for a routing path from a given one of the one or more source nodes to a given one of the two or more target nodes.
Converged Large Block And Structured Synthesis For High Performance Microprocessor Designs
View pageUS Patent:
8271920, Sep 18, 2012
Filed:
Aug 25, 2010
Appl. No.:
12/868086
Inventors:
Minsik Cho - Somers NY, US
Victor N. Kravets - White Plains NY, US
Smita Krishnaswamy - White Plains NY, US
Dorothy Kucar - White Plains NY, US
Jagannathan Narasimhan - Millwood NY, US
Ruchir Puri - Baldwin Place NY, US
Haifeng Qian - White Plains NY, US
Haoxing Ren - Austin TX, US
Chin Ngai Sze - Austin TX, US
Louise H. Trevillyan - Katonah NY, US
Hua Xiang - Ossining NY, US
Matthew M. Ziegler - Sleepy Hollow NY, US
Victor N. Kravets - White Plains NY, US
Smita Krishnaswamy - White Plains NY, US
Dorothy Kucar - White Plains NY, US
Jagannathan Narasimhan - Millwood NY, US
Ruchir Puri - Baldwin Place NY, US
Haifeng Qian - White Plains NY, US
Haoxing Ren - Austin TX, US
Chin Ngai Sze - Austin TX, US
Louise H. Trevillyan - Katonah NY, US
Hua Xiang - Ossining NY, US
Matthew M. Ziegler - Sleepy Hollow NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716110, 716104
Abstract:
Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.
Task-Based Multi-Process Design Synthesis With Reproducible Transforms
View pageUS Patent:
8341565, Dec 25, 2012
Filed:
Dec 20, 2010
Appl. No.:
12/972980
Inventors:
Anthony D. Drumm - Rochester MN, US
Jagannathan Narasimhan - Mount Kisco NY, US
Lakshmi N. Reddy - Briarcliff Manor NY, US
Louise H. Trevillyan - Katonah NY, US
Jagannathan Narasimhan - Mount Kisco NY, US
Lakshmi N. Reddy - Briarcliff Manor NY, US
Louise H. Trevillyan - Katonah NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716104, 716114, 716132, 716133, 716134, 716135
Abstract:
A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.
Task-Based Multi-Process Design Synthesis With Notification Of Transform Signatures
View pageUS Patent:
8392866, Mar 5, 2013
Filed:
Dec 20, 2010
Appl. No.:
12/972934
Inventors:
Anthony D. Drumm - Rochester MN, US
Frank J. Musante - Poughkeepsie NY, US
Jagannathan Narasimhan - Mount Kisco NY, US
Louise H. Trevillyan - Katonah NY, US
Frank J. Musante - Poughkeepsie NY, US
Jagannathan Narasimhan - Mount Kisco NY, US
Louise H. Trevillyan - Katonah NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716132, 716125, 716136
Abstract:
A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.
Task-Based Multi-Process Design Synthesis
View pageUS Patent:
8407652, Mar 26, 2013
Filed:
Dec 20, 2010
Appl. No.:
12/972879
Inventors:
Anthony D. Drumm - Rochester MN, US
Jagannathan Narasimhan - Mount Kisco NY, US
Lakshmi N. Reddy - Briarcliff Manor NY, US
Louise H. Trevillyan - Katonah NY, US
Brian C. Wilson - Rochester MN, US
Jagannathan Narasimhan - Mount Kisco NY, US
Lakshmi N. Reddy - Briarcliff Manor NY, US
Louise H. Trevillyan - Katonah NY, US
Brian C. Wilson - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716132, 716100, 716101, 716106, 716110
Abstract:
A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.
Net Routing
View pageUS Patent:
20070204255, Aug 30, 2007
Filed:
Feb 28, 2006
Appl. No.:
11/364382
Inventors:
Jagannathan Narasimhan - Millwood NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 17/50
US Classification:
716013000, 716005000
Abstract:
A solution for routing a net based on a slew and/or delay for one or more critical sinks in the net is provided. To this extent, the solution can generate electrical connection information for a circuit by generating a routing tree for each net in the circuit. When the net includes one or more critical sinks, a path to each sink in the net can be sequentially added to the routing tree. Each sink can be processed in an order of criticality, with non-critical sinks being processed last. The path to each sink is selected based on its impact to the slew and/or delay of each critical sink currently in the routing tree. For example, the path can be selected to minimize the highest slew and/or delay value for all of the critical sinks in the routing tree. In this manner, an improved routing tree can be generated for each net that optimizes the slew and/or delay in the circuit.
Methods And Apparatus For Providing Flexible Timing-Driven Routing Trees
View pageUS Patent:
20080170514, Jul 17, 2008
Filed:
Mar 26, 2008
Appl. No.:
12/055888
Inventors:
Renato Fernandes Hentschke - Porto Alegre, BR
Marcelo De Oliveira Johann - Porto Alegre, BR
Jagannathan Narasimhan - Millwood NY, US
Ricardo Augusto De Luz Reis - Porto Alegre, BR
Marcelo De Oliveira Johann - Porto Alegre, BR
Jagannathan Narasimhan - Millwood NY, US
Ricardo Augusto De Luz Reis - Porto Alegre, BR
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04L 12/28
US Classification:
370256
Abstract:
A method of producing a flexible timing-driven routing tree is provided. Two or more target nodes are sorted in accordance with data criticality. A source-sink grid is built from one or more source nodes and the two or more target nodes. An initial routing tree is built comprising the one or more source nodes. A routing tree generation algorithm is executed on the initial routing tree, utilizing the sorted two or more target nodes and the source-sink grid in accordance with a user-defined timing factor to construct a flexible timing-driven routing tree. The user-defined timing factor specifies an extent of isolation for a routing path from a given one of the one or more source nodes to a given one of the two or more target nodes.