Jeff B Kim

8581348, Nov 12, 2013

Dec 13, 2011

13/324699

Mahbub Rashed - Santa Clara CA, US
Steven Soss - Cornwall NY, US
Jongwook Kye - Pleasanton CA, US
Irene Y. Lin - Los Altos Hills CA, US
James Benjamin Gullette - Wadesboro NC, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Marc Tarabbia - Pleasant Valley NY, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

GLOBALFOUNDRIES, Inc. - Grand Cayman

H01L 27/088
H01L 21/70
H01L 21/02

257401, 257368, 257369, 257382, 257384

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

8618607, Dec 31, 2013

Jul 2, 2012

13/539830

Mahbub Rashed - Santa Clara CA, US
David Doman - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Irene Lin - Los Altos Hills CA, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Steve Soss - Cornwall NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Malta NY, US

GLOBALFOUNDRIES Inc. - Grand Cayman

H01L 21/02

257359, 257369, 257379, 257E21602, 257E21656, 257E23144, 257E23152, 257E27029, 257E27081, 257E29226, 257E29276

One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

20130146986, Jun 13, 2013

Dec 13, 2011

13/324740

Mahbub Rashed - Santa Clara CA, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

H01L 27/092
H01L 27/088

257369, 257368, 257E27062, 257E2706

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

20220367360, Nov 17, 2022

Aug 2, 2022

17/879574

- Malta NY, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

H01L 23/535
H01L 21/8234
H01L 27/02
H01L 21/768
H01L 21/285
H01L 21/8238
H01L 23/532
H01L 27/092
H01L 29/08

A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

20210013150, Jan 14, 2021

Sep 30, 2020

17/039187

- Grand Cayman, KY
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

H01L 23/535
H01L 21/8234
H01L 27/02
H01L 21/768
H01L 21/285
H01L 21/8238
H01L 23/532
H01L 27/092
H01L 29/08

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.

20190326219, Oct 24, 2019

Jul 3, 2019

16/502521

Mahbub Rashed - Santa Clara CA, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

H01L 23/535
H01L 29/08
H01L 27/092
H01L 23/532
H01L 21/8238
H01L 21/8234
H01L 21/285
H01L 27/02
H01L 21/768

A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

20160268204, Sep 15, 2016

May 25, 2016

15/164114

- Grand Cayman, KY
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

H01L 23/535
H01L 29/08
H01L 27/092
H01L 23/532
H01L 21/8238
H01L 21/285

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.