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Joseph M Mckinnerney

from Tampa, FL
Age ~62
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Also known as:
Joseph Mark Mckinnerney, Mark J Mckinnerney, Joe M Mckinnerney, Joseph M Mckinner, Jo Mckinnerney, Joseph Mc, Joseph Mc Kinnerney
Phone and address:
11653 Renaissance View Ct, Tampa, FL 33626
(813) 814-2131
Connected to:
Adarphus Mckinney, 80Adrienne D Mckinney, 54Almeda Mckinney, 108Amanda Mckinnerney, 38Ann H Mckinney, 91Annaliza D Mckinney, 53Antwana Mckinney, 39Aurelia Mckinney, 95Berth M Mckinney, 100Billie G Mckinnerney, 99

Joseph Mckinnerney Phones & Addresses

  • 11653 Renaissance View Ct, Tampa, FL 33626 (813) 814-2131
  • Indian Rocks Beach, FL
  • Pinellas Park, FL
  • 500 Belcher Rd S, Largo, FL 33771
  • 9760 106Th St, Largo, FL 33773 (727) 398-1572 (727) 398-2180
  • Seminole, FL

Work

Company: Honeywell Sep 1995 Position: Senior product design engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: University of South Florida 1992 to 1995 Specialities: Chemical Engineering

Skills

Powder X Ray Diffraction • Scanning Electron Microscopy • Six Sigma • Spectroscopy • Failure Analysis • Root Cause Analysis • Manufacturing Engineering • Engineering • Systems Engineering • Surface Chemistry • Xps • Engineering Management • Aerospace • Lean Manufacturing • Manufacturing • Dmaic • Xrf • X Ray • Fmea • Design of Experiments • Semiconductors • Continuous Improvement • Spc • Kaizen • Process Engineering • Iso • Value Stream Mapping

Industries

Aviation & Aerospace

Resumes

Resumes

Joseph Mckinnerney Photo 1

Tampa And St Petersburg, Florida Area

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Location:
Tampa, FL
Industry:
Aviation & Aerospace
Work:
Honeywell
Senior Product Design Engineer

Tampa and St Petersburg, Florida Area
Education:
University of South Florida 1992 - 1995
Bachelors, Bachelor of Science, Chemical Engineering
Skills:
Powder X Ray Diffraction
Scanning Electron Microscopy
Six Sigma
Spectroscopy
Failure Analysis
Root Cause Analysis
Manufacturing Engineering
Engineering
Systems Engineering
Surface Chemistry
Xps
Engineering Management
Aerospace
Lean Manufacturing
Manufacturing
Dmaic
Xrf
X Ray
Fmea
Design of Experiments
Semiconductors
Continuous Improvement
Spc
Kaizen
Process Engineering
Iso
Value Stream Mapping

Publications

Us Patents

Method And Apparatus For Applying External Coating To Grid Array Packages For Increased Reliability And Performance

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US Patent:
7645633, Jan 12, 2010
Filed:
Feb 7, 2008
Appl. No.:
12/027385
Inventors:
David A. Barnes - Palm Harbor FL, US
Jason C. Grooms - Petersburg FL, US
Neal B. Martinez - Maderia Beach FL, US
Joseph M. McKinnerney - Tampa FL, US
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H01L 21/44
US Classification:
438106, 257E3306
Abstract:
A method for coating a surface mount package is provided. The method includes applying a layer of a coating material above at least one surface of the surface mount package, applying a masking material above the layer of coating material, and removing the layer of coating material from a selected portion of the surface mount package defined by the masking material.

Method And Apparatus For Applying External Coating To Grid Array Packages For Increased Reliability And Performance

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US Patent:
20060278971, Dec 14, 2006
Filed:
Jun 10, 2005
Appl. No.:
11/150450
Inventors:
David Barnes - Palm Harbor FL, US
Jason Grooms - St. Petersburg FL, US
Neal Martinez - Maderia Beach FL, US
Joseph McKinnerney - Tampa FL, US
Assignee:
HONEYWELL INTERNATIONAL INC. - MORRISTOWN NJ
International Classification:
H01L 23/053
US Classification:
257701000
Abstract:
A method and apparatus are disclosed for selective removal of a conformal coating from the solder balls of grid array packages such that the benefits of the coating are realized. An ancillary benefit of the invention is improved process-ability of the grid array package by improving the mechanical containment of the solder during the reflow process and improved electrical isolation between the individual solder attachment points. For example, a method for coating a ball grid array is provided, which includes coating the ball grid array with a thin layer of parylene. Next, the solder ball side of the part is butter smeared or squeegeed with a water soluble coating and assembled wet. A mask having holes in the same pattern as the balls in the grid, and a thickness that is about 80% of the height of the balls, is applied to the solder ball side of the part. This side of the part is then butter smeared again with the water soluble coating, and the entire assembly is allowed to dry. At this point, about 20% of each parylene-coated solder ball protrudes higher than the surface of the mask. The solder ball side of the part is then grit blasted with an abrasive material. The extent that the abrasive material removes the parylene coating from the solder balls is limited by the mask and the layer of water soluble coating. Therefore, the grit blasting removes the parylene coating from only the protruding areas (e.g., about top 20%) of the solder balls. Water is then used to remove the water soluble coating, and the parylene coated part is baked to remove moisture. Thus, a parylene coated ball grid array (or column grid array) is provided that is highly impervious to moisture, has a very high dielectric strength, and thereby improves the electrical performance and reliability of the surface mounted part.
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Joseph M Mckinnerney from Tampa, FL, age ~62 Get Report