Michael N West

6339434, Jan 15, 2002

Nov 23, 1998

09/198314

Michael G. West - Portland OR
Robert Y. Greenberg - Portland OR
Alan L. Zimmerman - Portland OR

Pixelworks - Tualatin OR

G09G 500

345667, 348581

An image scaling circuit for increasing or decreasing the size of a sampled image to match a fixed resolution display. The circuit includes means for resizing the image in the horizontal and vertical dimension using independent sample rate converters. The sample rate converters increase or decrease the image size by a factor of Lx/Mx in the horizontal dimension and Ly/My in the vertical dimension where Lx and Ly are integers and Mx and My are decimal numbers of arbitrary precision to provide fine scaling control. In addition, image warping is conveniently implemented by varying the down sample ratios Mx and My on a pixel by pixel and/or line by line basis.

6611260, Aug 26, 2003

May 17, 1999

09/313060

Robert Y. Greenberg - Portland OR
Michael G. West - Portland OR

Pixelworks, Inc - Tualatin OR

G09G 500

345204, 345212, 345213

The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers.

6683604, Jan 27, 2004

Apr 4, 2001

09/826493

Michael G. West - Portland OR
Jamie J. LeVasseur - Vancouver WA

Pixelworks, Inc. - Tualatin OR

G09G 502

345204, 345699

A system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input frame rate and/or input resolution. The packing circuit generates coded image data by compressing the input image data. An unpacking circuit decompresses the coded image and provides output image data to a display device at an output frame rate and/or output resolution.

RE38618, Oct 12, 2004

Sep 8, 2000

09/660435

Michael G. West - Portland OR

InFocus Corporation - Wilsonville OR

H04N 512

348537, 348536, 348540

A method for producing a digital video signal from an analog video signal, the analog video signal including an analog video data signal that is raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (H ) that controls a line scan rate, and a vertical synchronizing signal (V ) that controls a frame refresh rate, to produce consecutive frames of video information, wherein the digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the video image producible by the analog video signal is calculated. The actual width W is compared with the expected width E.

6903733, Jun 7, 2005

Apr 1, 2003

10/405775

Robert Y. Greenberg - Portland OR, US
Michael G. West - Portland OR, US

Pixelworks, Inc. - Tualatin OR

G09G005/00

345204, 345212, 345213

The image scaling memory system of the present invention eliminates the use of internal or external line memories by using an existing frame memory coupled with an input buffer and a plurality of output buffers for providing a vertical scalar with simultaneous parallel access to multiple lines of data. Additionally, the image scaling memory system of the present invention, including the frame memory, is embedded into an integrated circuit. Thus, the image scaling circuit of the present invention improves reliability, lowers cost, and improves silicon area usage. The frame memory is coupled to an input buffer at an input side and a plurality of output buffers at an output side. The plurality of output buffers is positioned between the frame memory and the vertical scalar. Each output buffer sequentially gains access to and transfers portions of image lines from the frame buffer. Each output buffer stores only a portion of an image line resulting in relatively small output buffers.

6917366, Jul 12, 2005

Apr 4, 2001

09/826538

Michael G. West - Portland OR, US
Jamie J. LeVasseur - Vancouver WA, US

Pixelworks, Inc. - Tualatin OR

G09G005/36

345558, 345505, 345559, 370537

A system and method is provided for aligning multi-channel coded data over multiple clock periods. Data is received through a plurality of data channels and stored in a plurality of latches or queues. Data is scanned to determine whether a valid data transition has occurred. Once a valid transition is detected on all of the plurality of data channels, data is substantially simultaneously read out of the latches or queues resulting in synchronized or aligned data being provided at the output.

7002566, Feb 21, 2006

Dec 3, 2003

10/728241

Michael G. West - Portland OR, US
Jamie J. LeVasseur - Vancouver WA, US

Pixelworks, Inc. - Tualatin OR

G09G 5/007

345204, 345589

A system including a failsafe mechanism adapted to visually display frame locked digital image data and a method therefor. The system receives input image data at an input frame rate and/or input resolution. The packing circuit generates coded image data by compressing the input image data. An unpacking circuit decompresses the coded image and provides output image data to a display device at an output frame rate and/or output resolution.

RE40675, Mar 24, 2009

May 20, 2004

10/851979

Michael G. West - Portland OR, US

Infocus Corporation - Wilsonville OR

H04N 5/04
H04N 5/12
H04N 5/46
H04N 5/74
G09G 5/08

348537, 348536, 348540, 348 E5021, 348 E5114, 348 E5141

p-00010000.