Navinchandra A Kalidas

6396136, May 28, 2002

Dec 22, 1999

09/469476

Navinchandra Kalidas - Houston TX
Masood Murtuza - Sugarland TX
Raymond W. Thompson - Sugarland TX

Texas Instruments Incorporated - Dallas TX

H01L 2352

257691, 257698, 257700, 257737, 257738, 257780, 257778, 257712

A package for a flip chip integrated circuit including an interposer with electrical interconnecting for signal, power, and ground contacts. Routing is accomplished on only two conductor layers through the use of selective planes and buses. Multiple power planes are provided on a single conductor level to support circuits having different operating voltages. A unique cavity down BGA package for a flip chip interconnected integrated circuit is provided by adhering the interposer to a thermally conductive stiffener or base, and using solder balls to attach the frame to the base and interposer. The assemblage forms a chip cavity with interconnecting vias to external BGA solder balls terminals located in the perimeter frame.

6794743, Sep 21, 2004

Aug 3, 2000

09/631198

Michael A. Lamson - Westminster TX
Navinchandra Kalidas - Houston TX

Texas Instruments Incorporated - Dallas TX

H01L 2352

257691, 257698, 257700, 257737, 257738, 257778

A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias. Said signal lines being distributed relative to said first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and minimized effective self-inductance. Said signal lines further being electromagnetically coupled to said ground metal such that cross talk between signal lines is minimized.

6995037, Feb 7, 2006

Dec 1, 2003

10/724497

Michael A. Lamson - Westminster TX, US
Navinchandra Kalidas - Houston TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/44

438106, 438108, 438125

A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias. Said signal lines being distributed relative to said first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and minimized effective self-inductance. Said signal lines further being electromagnetically coupled to said ground metal such that cross talk between signal lines is minimized.

7135781, Nov 14, 2006

Aug 10, 2004

10/916194

Navinchandra Kalidas - Houston TX, US
Jeremias P. Libres - Garland TX, US
Michael P. Pierce - Plano TX, US

Texas Instruments Incorporated - Dallas TX

H01L 23/48
H01L 23/10

257783, 257707

Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate () with first and second surfaces (), at least one opening (), and a certain thickness (). On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads (); at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body () attached. A semiconductor chip () is positioned in the opening while leaving a gap () to the substrate; the chip has an active surface () including at least one bond pad (), and a passive surface () substantially coplanar with the second substrate surface (). Substrate thickness and chip thickness may be substantially equal. Bonding elements () bridge the gap to connect electrically bond pad and routing strip. Encapsulation material () protects the active chip surface and the bonding elements, and fills the gap so that the filler surface () is substantially coplanar with the passive chip surface and the second substrate surface.

7309648, Dec 18, 2007

Sep 6, 2006

11/470306

Navinchandra Kalidas - Houston TX, US
Jeremias P Libres - Garland TX, US
Michael P Pierce - Plano TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/44
H01L 21/48

438617, 438109, 438110, 438127, 257E23024, 257686

Disclosed is a semiconductor device that includes an electrically insulating, sheet-like substrate with first and second surfaces, at least one opening, and a certain thickness. On the first surface are a plurality of electrically conductive routing strips and a plurality of contact pads; at least one of the contact pads is electrically connected with at least one of the routing strips, and may have a solder body attached. A semiconductor chip is positioned in the opening while leaving a gap to the substrate; the chip has an active surface including at least one bond pad, and a passive surface substantially coplanar with the second substrate surface. Substrate thickness and chip thickness may be substantially equal. Bonding elements bridge the gap to connect electrically bond pad and routing strip. Encapsulation material protects the active chip surface and the bonding elements, and fills the gap so that the filler surface is substantially coplanar with the passive chip surface and the second substrate surface.

7795072, Sep 14, 2010

Apr 9, 2008

12/080961

Michael A. Lamson - Westminster TX, US
Navinchandra Kalidas - Houston TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/48

438106, 438108, 438121, 257E21506, 716 5

A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias. Said signal lines being distributed relative to said first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and minimized effective self-inductance. Said signal lines further being electromagnetically coupled to said ground metal such that cross talk between signal lines is minimized.

20050093170, May 5, 2005

Oct 29, 2003

10/695714

Navinchandra Kalidas - Houston TX, US
Jeremias Libres - Garland TX, US

Texas Instruments Incorporated - Dallas TX

H01L021/44
H01L023/52

257778000, 257787000, 438108000

An integrated interconnect package for a semiconductor die and a method for assembling the die into the integrated interconnect package. The method may comprise placing the active face of the die onto an adhesive disposed on a sacrificial carrier, and applying an encapsulant over the backside of the die, forming a substantially rigid assembly structure. The assembly structure is separated from the adhesive, and an insulating material is applied to the active face of the die and patterned by a photolithography operation, creating at least one opening through the insulating material for exposing at least one die bond pad. A conductive material is then applied over the insulating material, flowing into the openings to contact the bond pads. The conductive material is then patterned by a photolithography operation, removing at least a portion of the conductive material to create a plurality of electrical traces and package terminals.

20060063304, Mar 23, 2006

Nov 7, 2005

11/268072

Michael Lamson - Westminster TX, US
Navinchandra Kalidas - Houston TX, US

H01L 21/50
H01L 21/48

438106000, 438123000, 438121000

A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias. Said signal lines being distributed relative to said first power lines such that the inductive coupling between them reaches at least a minimum value, providing high mutual inductances and minimized effective self-inductance. Said signal lines further being electromagnetically coupled to said ground metal such that cross talk between signal lines is minimized. And an outermost insulating film protecting the exposed surfaces of said signal and power lines, said film having a plurality of openings filled with metal suitable for contacting selected signal and power lines and chip solder bumps.