Search

Paul Robertson Phones & Addresses

  • 5908 Kevin Kelly Pl, Austin, TX 78727
  • Kyle, TX
  • Lago Vista, TX
  • Lexington, KY
  • Champaign, IL

Professional Records

Lawyers & Attorneys

Paul Robertson Photo 1

Paul Robertson - Lawyer

View page
Specialties:
Arbitration
Complex Commercial Litigation
Products Liability
Management and Discovery of Electronic Documents
ISLN:
900796898
Admitted:
1992
University:
Princeton University, A.B., 1987
Law School:
Boston University, J.D., 1992

License Records

Paul A. Robertson

License #:
PST.009672 - Expired
Issued Date:
Nov 21, 1969
Expiration Date:
Dec 31, 2006
Type:
Pharmacist

Medicine Doctors

Paul Robertson Photo 2

Paul A. Robertson

View page
Specialties:
Hematology/Oncology
Work:
Providence Medical GroupProvidence Regional Cancer System
954 Anderson Dr STE 102, Aberdeen, WA 98520
(360) 533-6906 (phone), (360) 533-7962 (fax)

Providence Medical GroupProvidence Regional Cancer System
4525 3 Ave SE STE 200, Lacey, WA 98503
(360) 754-3934 (phone), (360) 943-8023 (fax)

Providence Medical GroupProvidence Regional Cancer System
2026 Olympic Hwy N STE 203, Shelton, WA 98584
(360) 754-3934 (phone), (360) 943-8023 (fax)
Education:
Medical School
University of Utah School of Medicine
Graduated: 1983
Procedures:
Chemotherapy
Conditions:
Anemia
Leukemia
Malignant Neoplasm of Female Breast
Multiple Myeloma
Non-Hodgkin's Lymphoma
Languages:
English
Spanish
Description:
Dr. Robertson graduated from the University of Utah School of Medicine in 1983. He works in Lacey, WA and 2 other locations and specializes in Hematology/Oncology. Dr. Robertson is affiliated with Capital Medical Center, Grays Harbor Community Hospital, Group Health Cooperative Central, Mason General Hospital, Providence Centralia Hospital, Providence Regional Medical Center Everett and

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mr. Paul Robertson
Ownership Exchange Group
Timeshare Resale and Rental Marketing
6742 Forest Hill Blvd., Suite 147, West Palm Beach, FL 33413
(561) 441-2720
Mr. Paul Robertson
Owner
Cutting Edge Carpentry & Renovations
Contractors - General
88 Havenwood Pl, Whitby, ON L1N 9V7
(905) 665-6314
Paul Robertson
Manager
Budget Brake & Muffler
Sur-del Brake & Muffler
Automobile Repairing & Service. Mufflers & Exhaust Systems-Engine. Brake Service
8038 120 St, Surrey, BC V3W 3N3
(604) 596-9581, (604) 596-3155
Paul Robertson
Owner
Afton Boat Transport, Inc.
Boat Transporting
PO Box 5, 2718 Saint Croix Trl S, Afton, MN 55001-0005
(651) 436-6892
Paul Robertson
President
Key West Locksmiths Ltd
Locks & Locksmiths
175 11780 River Rd, Richmond, BC V6X 1Z7
(604) 270-4355, (604) 270-4301
Paul Robertson
Owner
Afton Boat Storage Co.
Boat Storage. Boat Repair. Boat Transporting
PO Box 5, 2718 Saint Croix Trl S, Afton, MN 55001-0005
(651) 436-6892
Paul Robertson
Owner
Cutting Edge Carpentry & Renovations
Contractors - General
(905) 665-6314
Paul Robertson
President
Key West Locksmiths Ltd
Locks & Locksmiths
(604) 270-4355, (604) 270-4301

Publications

Wikipedia References

Paul Robertson Photo 3

Paul W . Robertson

Work:
Position:

Vice president • President

Education:
Area of science:

Marketing

Professions and applied sciences:

Television • Marketing

Skills & Activities:
Activity:

Entertainment

Isbn (Books And Publications)

Economic Relations Between Britain and Australasia, 1945-1970

View page
Author

Paul L. Robertson

ISBN #

0333919416

A Bite Out of the Apple

View page
Author

Paul E. Robertson

ISBN #

0741434210

God So Loved the World: Traditional Baptists and Calvinism

View page
Author

Paul E. Robertson

ISBN #

0914520423

Image to Interpretation: An Intelligent System to Aid Historians in Reading the Vindolanda Texts

View page
Author

Paul Robertson

ISBN #

0199204551

Dynamic Object Technology Clearly Explained

View page
Author

Paul Robertson

ISBN #

0124903401

The British Shipbuilding Industry, 1870-1914

View page
Author

Paul Robertson

ISBN #

0674082877

The Power of the Land: Identity, Ethnicity, and Class Among the Oglala Lakota

View page
Author

Paul Robertson

ISBN #

0815335911

Self-Adaptive Software: First International Workshop, Iwsas 2000, Oxford, Uk, April 17-19, 2000 Revised Papers

View page
Author

Paul Robertson

ISBN #

3540416552

Us Patents

Apparatus And Method Of Allowing Pci V1.0 Devices To Work In Pci V2.0 Compliant System

View page
US Patent:
6519555, Feb 11, 2003
Filed:
Sep 30, 1996
Appl. No.:
08/723174
Inventors:
Richard Allen Kelley - Apex NC
Danny Marvin Neal - Round Rock TX
Michael Anthony Perez - Cedar Park TX
Paul Gordon Robertson - Austin TX
Padmavathy Tamirisa - Austin TX
John Daniel Upton - Georgetown TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
703 13, 703 15
Abstract:
The invention provides an apparatus and method of allowing a device to respond to a configuration query only if it is the true target of the query. In one embodiment of the invention, logic gates having two inputs are provided. The first input of the logic gates is connected to the signal of a bridge that selects a device when the address of the signal is referenced in the configuration query. The second input of the logic gate receives a signal indicating whether the local bus or the subordinate bus is being configured and the output of the logic gate is used to enable the device. In a second embodiment, certain signals designated to indicate the selection of a bus are used to enable devices to respond to configuration queries.

System For Monitoring And Detecting Difference Voltage Levels Of I/O Adapter Cards Via A Connector

View page
US Patent:
6529967, Mar 4, 2003
Filed:
Sep 9, 1999
Appl. No.:
09/392836
Inventors:
Paul Gordon Robertson - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
710 16, 710 15, 710 62, 710 63, 710102, 713300, 439 55
Abstract:
A system and method are provided for detecting when a valid configuration of I/O adapters is present in the system board of a computer. The present invention is a mechanism that allows the system user to determine the configuration of the I/O adapter cards to be used, independent of their voltage levels. More particularly, if the programmed voltage of the computer system power supply is compatible with the desired adapter card, the present invention will allow the card to be inserted and used. The present invention includes a connector that is physically capable of receiving any one of a variety of adapter cards, independent of the operating voltage level of the adapter cards. The present invention is a mechanism for detecting a valid mix of adapter cards inserted into connectors on the system board of a computer. When adapter cards having different voltage ratings are inserted into the slots, power on operations are not allowed preventing possible damage to the computer.

Apparatus And Method For Providing A Transient Port

View page
US Patent:
6577905, Jun 10, 2003
Filed:
Jun 29, 2000
Appl. No.:
09/606639
Inventors:
Paul Gordon Robertson - Austin TX
Hector Saenz - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G05B 1500
US Classification:
700 1, 700 7, 700 11, 710107, 710108, 710118, 361110, 361111, 439225, 439579, 439620
Abstract:
An apparatus and method for providing a transient connection port are provided. Further, an apparatus and method for switching between a permanent connection port and a transient connection port are provided. The apparatus and method include a permanent connection port and a transient connection port located at the rear of a rack mounted server system and the front of the rack mounted server system, respectively. The permanent connection port operates when there is an absence of a connected device at the transient connection port. When a device is connected to the transient connection port, a signal is sent to a logic switch which causes the active input to be switched from the permanent connection port to the transient connection port. When the device is no longer connected to the transient connection port, the absence of the signal from the transient connection port causes the logic switch to switch the active input back to the permanent connection port.

Method And Apparatus For Enabling Cache Streaming

View page
US Patent:
60094826, Dec 28, 1999
Filed:
Mar 28, 1997
Appl. No.:
8/829554
Inventors:
Paul Gordon Robertson - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
G06F 1300
US Classification:
710 35
Abstract:
A process and implementing computer system in which an arbitration circuit is comprised of a plurality of state machines 301, 303 and 305 which combine to receive various system timing signals and provide a data bus grant signal effective to enable data streaming of sequential data blocks of information from an L2 cache memory 109 without intervening wait states between the data blocks.

Cache Module Fault Isolation Techniques

View page
US Patent:
58056068, Sep 8, 1998
Filed:
Mar 13, 1997
Appl. No.:
8/816627
Inventors:
Paul Gordon Robertson - Austin TX
Robert Lisin Tung - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1100
US Classification:
371 211
Abstract:
A process and implementing system is provided for conducting a memory test for isolating and identifying failed cache memory modules in a memory subsystem of a computer system. The methodology initially selects 303 a block of memory which is twice the size of the cache 105 being tested. The cache 105 is then disabled 305 and a first test is performed 307 on the selected block of to isolate byte addresses of individual bit failures. If bit failures are detected 308, the appropriate byte address is mapped 310 and the test is ended 321. If no bit errors are detected in the first test, the cache is enabled 309 and a second test is performed and the block is tested 311 for failures. Any detected failures are assumed to be cache failures and the appropriate byte address is mapped 315. The cache is again disabled 317. An appropriate message is then displayed 319 to indicate the results of the testing.

Method For Avoiding Livelock On Bus Bridge

View page
US Patent:
57348464, Mar 31, 1998
Filed:
Feb 26, 1996
Appl. No.:
8/606913
Inventors:
Paul Gordon Robertson - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1336
G06F 1340
US Classification:
395273
Abstract:
A method prevents a livelock condition from occurring between a host bus bridge (e. g. , memory controller) and a PCI bus bridge, where the host bus bridge and PCI bus bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1. 0 and PCI Local Bus Specification 2. The method includes the first step of masking from the PCI bridge a request generated by a device on a second bus. The second step includes requesting that the host bus bridge flush all existing I/O requests and postpone any future I/O requests from a central processing unit. The third step includes, in response to a notification from the host bus bridge that all I/O requests have been flushed and that any future I/O requests from the central processing unit will be postponed, unmasking the request to the PCI bridge. The fourth step includes, in response to unmasking the request to the PCI bus bridge, granting access of the second bus from the PCI bus bridge to the device. This method guarantees that any data posted in an internal write buffer of the bus bridge can be delivered to system memory.

Computer System And Arbitrator Utilizing A Bus Bridge That Avoids Livelock

View page
US Patent:
57782350, Jul 7, 1998
Filed:
Feb 26, 1996
Appl. No.:
8/606914
Inventors:
Paul Gordon Robertson - Austin TX
International Classification:
G06F 1314
G06F 13362
US Classification:
395728
Abstract:
A computer system and arbitrator prevent a livelock condition from occurring between a host bus bridge and a PCI bridge, where the host bus bridge and PCI bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1. 0 and PCI Local Bus Specification 2. The system includes an arbitrator for masking from the PCI bridge a request (REQ. sub. --) generated by a device on a second bus. The arbitrator requests that the host bus bridge flush all existing I/O requests (FLUSHREQ. sub. --) and postpone any future I/O requests from a central processing unit. The third step includes, in response to a notification from the host bus bridge that all I/O requests have been flushed and that any future I/O requests from the central processing unit will be postponed (MEMACK. sub. --), the arbitrator unmasks the request to the PCI bridge (GREQ. sub. --). In response to unmasking the request to the PCI bridge, the PCI bridge grants control of the second bus to the device (GNT. sub. --).

Method For Avoiding Livelock On Bus Bridge Receiving Multiple Requests

View page
US Patent:
57178763, Feb 10, 1998
Filed:
Feb 26, 1996
Appl. No.:
8/606912
Inventors:
Paul Gordon Robertson - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
G06F 1340
US Classification:
395309
Abstract:
A method prevents a livelock condition from occurring between a host bus bridge and a PCI bridge, where the host bus bridge and PCI bridge conform to the specification delineated in the PCI-to-PCI Bridge Architecture Specification 1. 0 and PCI Local Bus Specification 2. The method includes the first step of in response to at least first and second requests being substantially simultaneously received from at least first and second peripherals, determining if a state of a state machine corresponds to an assigned order of either the first peripheral or the second peripheral. The second step includes if the state does not correspond to the assigned order of the first peripheral or the second peripheral, advancing the state and repeating the first step until the state corresponds to one of the first or second peripherals. The third step includes if the state corresponds to the assigned order of either the first or second peripheral, determining if the selected request targets system memory. The fourth step includes if the selected request targets system memory, requesting the host bus bridge to flush all existing I/O requests and postpone any future I/O requests from a central processing unit.
Paul S Robertson from Austin, TX, age ~63 Get Report