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Prabhjot Singh Phones & Addresses

  • 1383 Danby Ave, San Jose, CA 95132 (408) 258-2344
  • 216 Montclair Ave, San Jose, CA 95116
  • 2911 Betsy Way, San Jose, CA 95133 (408) 937-4914
  • Hartford, CT
  • Dayville, CT
  • Santa Clara, CA
  • Davie, FL

Resumes

Resumes

Prabhjot Singh Photo 1

Prabhjot Singh Fremont, CA

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Work:
Carnegie Mellon University
Silicon Valley, CA
Sep 2012 to Nov 2012

Tata Consultancy Services
New Delhi, Delhi
2012 to 2012
Assistant Systems Engineer

NIT Jalandhar

Mar 2011 to May 2011

Sensifi Inc

2010 to 2011
Software Engineer

Sensifi Inc
Hyderabad, Andhra Pradesh
Jun 2010 to Aug 2010
Software Engineering Intern

Education:
National Institute of Technology
Jalandhar, Punjab
Jun 2011
Bachelor of Technology in Instrumentation and Control Engineering

Carnegie Mellon University
Mountain View, CA
Master of Science in Software Engineering and Development Management

Prabhjot Singh Photo 2

Prabhjot Singh Sunnyvale, CA

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Work:
Little caesar
San Jose, CA
Oct 2009 to Jul 2014
Manager

Education:
A.s
Punjab
2008 to 2009
High school

Prabhjot Singh Photo 3

Prabhjot Singh Mount Holly, NC

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Work:
Amcal Transportation Inc.
San Leandro, CA
Oct 2011 to Dec 2011
Dispatch

Biba Insurance Services, Inc.
Lathrop, CA
Nov 2010 to Jan 2011
Customer Service Representative

ACS
Anderson, IN
Sep 2009 to Aug 2010
Theft prevention, Customer Service

Allied Barton Security
Indianpolis, IN
Aug 2008 to Sep 2009
Security Guard

Wal Mart
Noblesville, IN
Nov 2007 to Feb 2008
Grocery Stocker

SGH Distributors
Corona, CA
Jan 1999 to Oct 2007
Courier

Education:
La Habra High School
La Habra, CA
2004
Diploma

Skills:
Motivated, quick learner, Customer service 12 years experience

Business Records

Name / Title
Company / Classification
Phones & Addresses
Prabhjot Singh
President
S.S TRUCKING HAUL INC
Local Trucking Operator
102 BOX FORD PL, San Ramon, CA 94583
750 Greenlaven St, Manteca, CA 95336
102 Boxford Pl, San Ramon, CA 94583
Prabhjot Singh
REFULGENT CONSULTING INC
Prabhjot Singh
President
PIXATEL SYSTEMS, INC
324 Genoa Dr, Redwood City, CA 94065
1020 Yates Way, San Mateo, CA 94403
1020 Marsh Rd, Menlo Park, CA 94025
1290 San Tomas Aquino Rd, San Jose, CA 95117

Publications

Us Patents

Flash Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

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US Patent:
7944745, May 17, 2011
Filed:
Feb 24, 2010
Appl. No.:
12/711520
Inventors:
Hosam Haggag - Mountain View CA, US
Alexander Kalnitsky - San Francisco CA, US
Edgardo Laber - San Jose CA, US
Prabhjot Singh - San Jose CA, US
Michael D. Church - Sebastian FL, US
Assignee:
Intersil Americas Inc. - Milpitas CA
International Classification:
G11C 11/34
G11C 16/04
US Classification:
36518508, 36518506, 3651851, 36518517, 36518528
Abstract:
A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

Flash Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

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US Patent:
8345488, Jan 1, 2013
Filed:
Apr 6, 2011
Appl. No.:
13/080814
Inventors:
Hosam Haggag - Mountain View CA, US
Alexander Kalnitsky - San Francisco CA, US
Edgardo Laber - San Jose CA, US
Prabhjot Singh - San Jose CA, US
Michael D. Church - Canyon Lake FL, US
Assignee:
Intersil Americas Inc. - Milpitas CA
International Classification:
G11C 16/04
US Classification:
36518529, 36518506, 36518508, 3651851
Abstract:
A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

Flash Memory Array Of Floating Gate-Based Non-Volatile Memory Cells

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US Patent:
20080266958, Oct 30, 2008
Filed:
Sep 25, 2007
Appl. No.:
11/861102
Inventors:
Hosam Haggag - Mountain View CA, US
Alexander Kalnitsky - San Francisco CA, US
Edgardo Laber - San Jose CA, US
Prabhjot Singh - San Jose CA, US
Michael D. Church - Sebastian FL, US
Assignee:
INTERSIL AMERICAS INC. - Milpitas CA
International Classification:
G11C 16/04
US Classification:
36518511, 36518528, 36518529
Abstract:
A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

Clock-Synced Transient Encryption

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US Patent:
20220286292, Sep 8, 2022
Filed:
May 26, 2022
Appl. No.:
17/804206
Inventors:
- San Francisco CA, US
Prabhjot SINGH - Union City CA, US
Assignee:
Salesforce, Inc. - San Francisco CA
International Classification:
H04L 9/32
H04L 9/40
H04L 9/08
Abstract:
A request for a transaction between a client system and a server system may be processed. The transaction may be associated with transmission of data between the client system and the server system. The data may be encrypted using a transient encryption key to form encrypted data. The transient encryption key may be a synced-clock random number configured to automatically change when a designated time interval elapses. The encrypted data may be transmitted between the client system and the server system.

Clock-Synced Transient Encryption

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US Patent:
20210036862, Feb 4, 2021
Filed:
Aug 2, 2019
Appl. No.:
16/530773
Inventors:
- San Francisco CA, US
Prabhjot Singh - Union City CA, US
Assignee:
Salesforce.com, Inc. - San Francisco CA
International Classification:
H04L 9/32
H04L 9/08
H04L 29/06
Abstract:
A request for a transaction between a client system and a server system may be processed. The transaction may be associated with transmission of data between the client system and the server system. The data may be encrypted using a transient encryption key to form encrypted data. The transient encryption key may be a synced-clock random number configured to automatically change when a designated time interval elapses. The encrypted data may be transmitted between the client system and the server system.

Current Sharing Scheme In Current Mode Control For Multiphase Dc-Dc Converter

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US Patent:
20200389092, Dec 10, 2020
Filed:
May 21, 2020
Appl. No.:
16/880814
Inventors:
- Milpitas CA, US
Prabhjot SINGH - San Jose CA, US
Long Robin YU - Zhejiang, CN
Assignee:
Renesas Electronics America Inc. - Milpitas CA
International Classification:
H02M 3/158
H02M 1/00
Abstract:
The present embodiments relate generally to DC-DC converters and more particularly to a scheme for providing current sharing between parallel converters in a multiphase configuration. In some embodiments, a cycle-by-cycle instant correction to the compensation signal offset is provided based on the current share error between the paralleled converters so as to achieve improved instant current share performance.

Cross Account Access For A Virtual Personal Assistant Via Voice Printing

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US Patent:
20200265842, Aug 20, 2020
Filed:
Feb 19, 2019
Appl. No.:
16/278967
Inventors:
- San Francisco CA, US
Prabhjot SINGH - Union City CA, US
International Classification:
G10L 15/32
G10L 15/22
G10L 17/00
G06F 9/451
G06F 21/32
Abstract:
A method for accessing a virtual personal assistant has been developed. First, a trust relationship is established between a primary smart speaker device that allows a user to access the virtual personal assistant with voice commands and a separate secondary smart speaker device. A trust relationship is established by generating a request at the secondary smart speaker device to allow access the virtual personal assistant with voice print authentication from the user and then validating the request at the primary smart speaker device to confirm the authenticity of the request. Next, a voice input is received from the user at the secondary smart speaker device requesting access to the virtual personal assistant. The identity of the user is verified using voice print identification with the secondary smart speaker device. Access for the user is then granted to the virtual personal assistant using the secondary smart speaker device.

Managing Access Credentials For A Service Provider

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US Patent:
20200053089, Feb 13, 2020
Filed:
Aug 8, 2018
Appl. No.:
16/058815
Inventors:
- San Francisco CA, US
Prabhjot SINGH - Union City CA, US
International Classification:
H04L 29/06
G06F 21/33
G06F 21/46
G06F 21/62
H04L 9/32
Abstract:
A computing device includes a memory and one or more processors coupled to the memory. The memory contains machine readable medium storing machine executable code which, when executed by the one or more processors, cause the one or more processors to: identify a service provider providing services or information to at least one of a plurality of organizations having access to a multi-tenant database system provided by a first party; establish an account for the service provider at a hosted service system, the hosted service system provided by a third party that is different from the first party providing the multi-tenant database system, the account for maintaining access credentials for the at least one of the plurality of organizations to the service provider's services or information, wherein the access credentials are not maintained at the multi-tenant database system; and using the credentials, authenticate the at least one of a plurality of organizations for access to the service provider's services or information through the multi-tenant database system. In some embodiments, the one or more processors create login credentials for the account and transmit the login credentials to the service provider so that the service provider may access the account
Prabhjot X Singh from San Jose, CA, age ~52 Get Report