Sang N Nguyen

6456539, Sep 24, 2002

Jul 12, 2001

09/903919

Sang Thanh Nguyen - Union City CA
Loc B. Hoang - San Jose CA
Hung Q. Nguyen - Fremont CA

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 700

36518907, 3651852, 36518521, 36518905, 365207

The present invention assures that valid and correct sensed data is latched before outputting from the memory device. The valid or correct sensed data is determined by the reference signal being first compared to two margin reference signals prior to latching the output of the comparator between the reference signal and the sensed signal from the selected memory cell. This maximizes the performance of the read operation as well as ensures the correct valid sense data is latched.

6490212, Dec 3, 2002

Jul 11, 2001

09/904160

Hung Q. Nguyen - Fremont CA
Nianglamching Hangzo - San Jose CA
Sang Thanh Nguyen - Union City CA

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 700

365207, 36518907, 365194, 365210

A memory device includes a sense circuit comprising a sense amplifier, a reference sense circuit and a comparator. The sense amplifier detects a signal on a bit line associated with a column of memory cells in a memory array. The reference sense circuit detects a signal on a reference bit line associated with a column of reference cells in the memory array. The comparator compares the outputs of the sense amplifier and the reference sense circuit and provides a signal indicative of the contents of the read memory cell. In response to a transition of an address, the bit line and the reference bit line are precharged prior to reading of the memory cell. The reference sense circuit includes a selectable load that is disabled during the initial time after the address transition so that the bit line and the reference bit line rises substantially identically and then enabled to allow the reference bit line to settle to a steady state.

6788595, Sep 7, 2004

Aug 5, 2002

10/213243

Hung Q. Nguyen - Fremont CA
Sang Thanh Nguyen - Union City CA
Loc B. Hoang - San Jose CA
Tam M. Nguyen - San Jose CA

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 700

365200, 365201

Predetermined data is stored in first and second predetermined locations of a memory. The first location may be in a first part of the memory, and the second location may be in a redundant part of the memory. At power up or reset, the first predetermined location of the memory successively is read and compared to data stored in a register until the comparison indicates a match for a predefined number of consecutive reads and comparisons. The successive reading may be stopped if the number of comparisons indicating a failure equals another predefined number of times. The data stored in the second predetermined location also is read. This data may be compared to the data previously read from the second predetermined location. The reading and comparing from the first predetermined location and the reading from the second predetermined location are continued until the number of times data is read from the second predetermined location equals a third predetermined number. The voltage signal is then determined to be valid after sufficient successive reads of the first predetermined location of the memory.

6853584, Feb 8, 2005

May 2, 2003

10/428742

Hung Q. Nguyen - Fremont CA, US
Sang Thanh Nguyen - Union City CA, US
Elbert Lin - Fremont CA, US
Anh Ly - San Jose CA, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C016/06

36518521, 365226

A non-volatile memory semiconductor device has a circuit to compensate for the variation in the data pattern to be programmed. The variation in the data patter creates a variation in the current requirement. The array receives a plurality of data pattern signals which affect the total amount of current flowing into a plurality of columns and into the memory array. A high voltage source generates an output which is supplied along a conducting path connected to the group of columns. A pass transistor is in the conducting path controlling the current flow in the conducting path. A current source has a first terminal and a second terminal with the first terminal connected to the output of the high voltage generator and the second terminal connected to the gate of the pass transistor. A plurality of current sources are collectively connected to a node. Each of the plurality of current sources receives a plurality of second signals with each second signal being an inverse of the first signal, and controlling the total amount of current flowing through the node.

7631231, Dec 8, 2009

Apr 19, 2006

11/407602

Sang Thanh Nguyen - Union City CA, US
Hieu Van Tran - San Jose CA, US
Hung O. Nguyen - Fremont CA, US
Phil Klotzkin - Springfield NJ, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 29/00
G01R 31/28
G11C 7/00

714718, 714734, 365201

In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.

8020055, Sep 13, 2011

Dec 2, 2009

12/629302

Sang Thanh Nguyen - Union City CA, US
Hieu Van Tran - San Jose CA, US
Hung O. Nguyen - Fremont CA, US
Phil Klotzkin - Springfield NJ, US

Silicon Storage Technology, Inc. - Sunnyvale CA

G11C 29/00
G11C 7/00

714718, 365201

In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.

8619459, Dec 31, 2013

May 25, 2012

13/481696

Sang Nguyen - Union City CA, US
Hagop Nazarian - San Jose CA, US

Crossbar, Inc. - Santa Clara CA

G11C 11/00
G11C 5/06
G11C 7/00
G11C 7/02

365148, 365 63, 365163, 36518915, 365205, 365207

Providing for resistive random access memory (RRAM) having high read speeds is described herein. By way of example, a RRAM memory can be powered at one terminal by a bitline, and connected at another terminal to a gate of a transistor having a low gate capacitance (relative to a capacitance of the bitline). With this arrangement, a signal applied at the bitline can quickly switch the transistor gate, in response to the RRAM memory being in a conductive state. A sensing circuit configured to measure the transistor can detect a change in current, voltage, etc. , of the transistor and determine a state of the RRAM memory from the measurement. Moreover, this measurement can occur very quickly due to the low capacitance of the transistor gate, greatly improving the read speed of RRAM.

6414522, Jul 2, 2002

Sep 14, 2000

09/661681

Hung Q. Nguyen - Fremont CA
Sang Nguyen - Oakland CA

Silicon Storage Technology, Inc. - Sunnyvale CA

H03C 300

327101, 327157, 327277, 331 57, 331185

In an improved charge pump bias generating circuit for a charge pump for a semiconductor integrated circuit device, the pump has a bias generator which has an input for receiving a pump enable signal. The bias generator generates a ramped bias signal in response to the pump enable signal. A voltage controlled oscillator has an input to receive the ramped bias signal and generates an oscillating signal having a frequency which is dependent upon the voltage of the ramped bias signal. As a result, the sudden turn on of the pump enable signal would cause a gradual turn on of the voltage controlled oscillator gradually turning on the clock output signal from the voltage oscillator, thereby reducing power surge in the circuit.