Sean R Mclaughlin

7737534, Jun 15, 2010

Jun 10, 2008

12/136193

Sean R. McLaughlin - Severn MD, US
Narsingh Bahadur Singh - Ellicott City MD, US
Brian Wagner - Baltimore MD, US
Andre Berghmans - Owing Mills MD, US
David J. Knuteson - Ellicott City MD, US
David Kahler - Arbutus MD, US
Anthony A. Margarella - Columbia MD, US

Northrop Grumman Systems Corporation - Los Angeles CA

H01L 29/868

257656, 257E29085, 257E29336, 977774

A process is provided for fabricating a semiconductor device having a germanium nanofilm layer that is selectively deposited on a silicon substrate in discrete regions or patterns. A semiconductor device is also provided having a germanium film layer that is disposed in desired regions or having desired patterns that can be prepared in the absence of etching and patterning the germanium film layer. A process is also provided for preparing a semiconductor device having a silicon substrate having one conductivity type and a germanium nanofilm layer of a different conductivity type. Semiconductor devices are provided having selectively grown germanium nanofilm layer, such as diodes including light emitting diodes, photodetectors, and like. The method can also be used to make advanced semiconductor devices such as CMOS devices, MOSFET devices, and the like.

20090283824, Nov 19, 2009

Oct 24, 2008

12/258236

Thomas J. Knight - Silver Spring MD, US
Eric J. Stewart - Silver Spring MD, US
Joseph T. Smith - Columbia MD, US
Sean McLaughlin - Severn MD, US
Narsingh B. Singh - Ellicott City MD, US

NORTHROP GRUMMAN SYSTEMS CORPORATION - Los Angeles CA

H01L 29/78
H01L 21/336

257335, 438286, 257E29256, 257E21417

In one embodiment, the disclosure relates to a low-power semiconductor switching device, having a substrate supporting thereon a semiconductor body; a source electrode coupled to the semiconductor body at a source interface region; a drain electrode coupled to the semiconductor body at a drain interface region; a gate oxide film formed over a region of the semiconductor body, the gate oxide film interfacing between a gate electrode and the semiconductor body; wherein at least one of the source interface region or the drain interface region defines a sharp junction into the semiconductor body.

20210392157, Dec 16, 2021

Aug 27, 2021

17/459908

- Seattle WA, US
Nikhil Reddy Cheruku - Falls Church VA, US
John Byron Cook - Brooklyn NY, US
Temesghen Kahsai Azene - Union City CA, US
William Jo Kocik - Charles Town WV, US
Sean McLaughlin - Seattle WA, US
Mark Edward Stalzer - Arlingon VA, US
Blake Whaley - Fairfax VA, US
Yiwen Wu - Fairfax VA, US

Amazon Technologies, Inc. - Seattle WA

H04L 29/06
G06F 16/2455
H04L 12/24
H04L 12/26

Methods, systems, and computer-readable media for automated packetless network reachability analysis are disclosed. An analysis is performed of network configuration data for a network comprising a host computer. Based at least in part on the analysis, one or more ports at the host computer that are reachable from another computer are determined. Based at least in part on the analysis, one or more routes to the one or more ports are determined. A report is generated that is descriptive of the one or more ports and the one or more routes.

20200007569, Jan 2, 2020

Jun 27, 2018

16/020865

- Seattle WA, US
Nikhil Reddy Cheruku - Falls Church VA, US
John Byron Cook - Brooklyn NY, US
Temesghen Kahsai Azene - Union City CA, US
William Jo Kocik - Charles Town WV, US
Sean McLaughlin - Seattle WA, US
Mark Edward Stalzer - Arlington VA, US
Blake Whaley - Fairfax VA, US
Yiwen Wu - Fairfax VA, US

Amazon Technologies, Inc. - Seattle WA

H04L 29/06
H04L 12/24
H04L 12/26
G06F 17/30

Methods, systems, and computer-readable media for automated packetless network reachability analysis are disclosed. An analysis is performed of network configuration data for a network comprising a host computer. Based at least in part on the analysis, one or more ports at the host computer that are reachable from another computer are determined. Based at least in part on the analysis, one or more routes to the one or more ports are determined. A report is generated that is descriptive of the one or more ports and the one or more routes.

20180351072, Dec 6, 2018

Jun 2, 2017

15/612326

CHRISTOPHER F. KIRBY - GAMBRILLS MD, US
VIVIEN M. LUU - LINTHICUM MD, US
MICHAEL RENNIE - ASHLAND VA, US
SEAN R. MCLAUGHLIN - SEVERN MD, US

NORTHROP GRUMMAN SYSTEMS CORPORATION - FALLS CHURCH VA

H01L 39/24
H01L 21/768
H01L 21/02
H01L 23/522
H01L 23/532

A method of forming a superconductor interconnect structure is disclosed. The method includes forming a dielectric layer overlying a substrate, forming an interconnect opening in the dielectric layer, and moving the substrate to a deposition chamber. The method further includes depositing a superconducting metal in the interconnect opening, by performing a series of superconducting deposition and cooling processes to maintain a chamber temperature at or below a predetermined temperature until the superconducting metal has a desired thickness, to form a superconducting element in the superconductor interconnect structure.