Sergio Salvador Ramirez

7986195, Jul 26, 2011

Feb 25, 2008

12/036377

Sergio R. Ramirez - Austin TX, US

Mentor Graphics Corporation - Wilsonville OR

H03C 3/00

332119, 332100, 332117, 332120, 455 42, 455110

Provided are apparatuses and methods for digital FM modulation. In one example, a message signal is integrated by an integrator to transform the message signal into a complex signal. The complex signal may include at least two complex components that may interfere to produce an FM modulated carrier signal. Hence, in this example, the method and apparatus for digital FM modulation may produce an FM modulated carrier signal without phase shifting. In another example, a lookup table is not necessary for modulation of the carrier signal.

57810532, Jul 14, 1998

Aug 21, 1996

8/701016

Sergio R. Ramirez - Austin TX

Advanced Micro Devices Inc. - Sunnyvale CA

H03K 3037

327215

A positive edge triggered flip flop which includes a master stage and a slave stage. The master stage includes an inverter that receives a clock input (C), and a first NAND gate having one input port for receiving a data input (D). The master stage also includes a second NAND gate and a first NOR gate that have their respective output connected to an input port of the other gate. The slave stage receives an inverted clock output from the inverter of the master stage. The slave stage includes a third NAND gate and a second NOR gate that also have their respective output connected to an input port of the other gate. An output value (Y) is read from the output of the second NOR gate.

54955130, Feb 27, 1996

Nov 18, 1994

8/343990

Sergio R. Ramirez - Austin TX
Imran Baoai - Austin TX

Advanced Micro Devices Inc. - Sunnyvale CA

H03K 2102
H03K 2344

377111

A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The latch circuit is formed of a first clocked half-latch, a second clocked half-latch and an inverter for storing a binary output signal. The first clocked half-latch is responsive to a first clock phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch is responsive to a second clock phase signal for transferring a binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The control circuit requires only one transistor and two input signals to perform its required functions. When the input complement signal is High and the first phase input clock signal is High, an enable signal is sent to the first clocked half-latch, thereby enabling the count process.

57606129, Jun 2, 1998

Aug 13, 1996

8/696087

Sergio R. Ramirez - Austin TX

Advanced Micro Devices Inc. - Sunnyvale CA

H03K 908

327 34

An inertial delay circuit includes a negative glitch removing circuit connected in series with a positive glitch removing circuit. The negative and positive glitch removing circuits are respectively configured to pass only negative and positive pulses of an input signal having a pulse width greater than a pre-determined width. The negative glitch removing circuit passes its input through a delay line and performs a logical OR on its input and the delayed signal. The positive glitch removing circuit passes its input through a delay line and performs a logical AND on its input and the delayed signal. The glitch removing circuits may further include respective pulse width restoring circuits to restore the pulses passing therethrough to their original widths.

54523451, Sep 19, 1995

Jan 21, 1994

8/184564

Yan Zhou - Austin TX
Merle L. Miller - Austin TX
V. Vijayakumaran Nair - Austin TX
Sergio Ramirez - Austin TX

Advanced Micro Devices - DE

H04M 1500
H04M 1538

379124

An apparatus for controlling the magnitude of a metering signal used in a communication system includes a high pass filter and a threshold detector. The apparatus is preferably integrated on to a subscriber line audio-processing circuit (SLAC device) which is used on a line card. The device is operable with either 12 kHz of 16 kHz metering signals. The high pass filter preferably includes a shift register and an adder. The level detector preferably includes a shift register, an OR gate and an AND gate. The device preferably is utilized to reduce the echo or reflection caused by the variable impedance of subscriber lines in telephone communication systems.

55149871, May 7, 1996

Jun 27, 1994

8/265930

Sergio R. Ramirez - Austin TX

Advanced Micro Devices Inc. - Sunnyvale CA

H03K 5153

327 74

A regenerative comparator provides the capability of operating faster than a traditional regenerative comparator and the hysteresis points can be individually set and fine tuned. The regenerative comparator includes a current mirror having an input transistor connected to first and second output transistors, a first and second reference current sources which are set at a first and second predetermined level, respectively. An outputs of the first and second output transistors are provided to the latch through an inverter. The output of the latch transitions from a first logical output state to a second logical output state when an input current increases from a magnitude less than the first predetermined level to a magnitude greater than the first predetermined level.

59828153, Nov 9, 1999

Jul 1, 1996

8/675297

Sergio R. Ramirez - Austin TX

Advanced Micro Devices Inc. - Sunnyvale CA

H04B 346
H04B 1700
H04Q 122

375224

An apparatus for setting a device into a test mode. The apparatus has a first input port for receiving a fixed, constant signal during a normal mode of the device, and for receiving a non-fixed, clocked signal so as to set the device into a test mode. The apparatus also has a second input port for receiving a non-fixed, clocked signal during the normal mode and for receiving a fixed, constant signal so as to set the device into the test mode. When both the first input port receives the non-fixed, clocked signal and the second input port receives the fixed, constant signal for a predetermined amount of time, the device is placed into the test mode.

56362730, Jun 3, 1997

Jun 7, 1995

8/483868

Walter S. Schopfer - Austin TX
Sergio R. Ramirez - Austin TX

H04M 302

379412

An apparatus for determining a power cross condition during a ringing state of a telephone. The apparatus also is capable of distinguishing a true power cross condition from a short loop ringing condition, by including a first path for receiving a signal indicative of a voltage across a ring feed resistor exceeding a predetermined value, and determining if that voltage is in an active state for a predetermined amount of time (i. e. , 14 milliseconds). The apparatus also includes a second path for receiving a first and second current that flow respectively across a first and second sense resistor connected to opposite ends of the ring feed resistor. On the second path, the first and second currents are subtracted, converted to a digital value, filtered, and compared to a threshold value to determine if a ring trip has occurred. If so, the potential ring trip is sent to a persistence timer circuit, for checking if it is in an active state for a predetermined amount of time (i. e. , 104 milliseconds).