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Terry G Lawell

from Austin, TX
Age ~82
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Also known as:
Terry Gunning Lawell, Terry Gunning Lowell, Terry Gunnin, Teray Lawell, Terry Y
Phone and address:
7434 Fireoak Dr, Austin, TX 78759
(512) 257-8438
Related to:
Alfredo Ibarra, 51
Connected to:
Elaine C Lawell, 77Lauren M Lawell, 28Lawrence T Lawell, 65Christopher R Lawellin, 34David K Lawen, 58Rica M Lawenko, 34Barney L Lawens, 48Delores J Lawens, 80Jason N Lawent, 49David B Lawentmann, 49

Terry Lawell Phones & Addresses

  • 7434 Fireoak Dr, Austin, TX 78759 (512) 257-8438
  • Spicewood, TX
  • 7434 Fireoak Dr, Austin, TX 78759 (512) 826-4125

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Emails

t***l@rediffmail.com

Resumes

Resumes

Terry Lawell Photo 1

Terry Lawell

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Location:
Austin, TX
Industry:
Automotive
Skills:
Product Marketing
Debugging
Functional Verification
Start Ups
Microprocessors
Processors
Asic
Business Development
Verilog
Cadence
Engineering
Embedded Systems
Fpga
Soc
Systemverilog
Semiconductors
Simulations
Digital Signal Processors
Wireless
Digital Signal
System Architecture
Ic
Terry Lawell Photo 2

Terry Lawell

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Terry Lawell Photo 3

Terry Lawell

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Publications

Us Patents

Data Processing System And Method Thereof

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US Patent:
55726895, Nov 5, 1996
Filed:
Mar 21, 1995
Appl. No.:
8/408045
Inventors:
Michael G. Gallup - Austin TX
L. Rodney Goke - Austin TX
Robert W. Seaton - Austin TX
Terry G. Lawell - Austin TX
Stephen G. Osborn - Austin TX
Thomas J. Tomazin - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 9315
US Classification:
395376
Abstract:
A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Packet-At-A-Time Reporting In A Data Link Controller

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US Patent:
48520888, Jul 25, 1989
Filed:
Apr 3, 1987
Appl. No.:
7/035817
Inventors:
Dale E. Gulick - Austin TX
Terry G. Lawell - Austin TX
Charles Crowe - Germantown TN
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H04J 324
H04B 156
US Classification:
370 94
Abstract:
A data link controller (DLC) 52 is disclosed which employs buffers (100,106) on both receive and transmit sides. These last-in, first-out buffers contain a position indicating that a character is the last one of a packet. In this way, a user need not monitor reception or transmission on a character-by-character basis, but need only concern themselves with packets. The receive and transmit FIFO's generate requests for more characters by monitoring the number of characters stored and thereby automatically receive and transmit characters without processor intervention. A four-stage mechanism (600,602,604,606,608,610,612,614) permits monitoring of multiple contiguous frames (back-to-back frames) received. Control of the DLC is provided by status and control registers (112,212) which are accessible to the user via a microprocessor interface (50). Particular registers have bit positions monitoring status conditions in such a manner that the most-probable one of a set of conditions compries the least-significant bit position, while the least-probable condition occupies the most-significant bit position.

Data Processing System And Method Thereof

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US Patent:
56008465, Feb 4, 1997
Filed:
Feb 17, 1995
Appl. No.:
8/390831
Inventors:
Michael G. Gallup - Austin TX
L. R. Goke - Austin TX
Robert W. Seaton - Austin TX
Terry G. Lawell - Austin TX
Assignee:
Motorola Inc. - Schaumburg IL
International Classification:
G06F 15347
US Classification:
395800
Abstract:
A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Data Link Controller With Flexible Multiplexer

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US Patent:
50480120, Sep 10, 1991
Filed:
Feb 14, 1989
Appl. No.:
7/311411
Inventors:
Dale E. Gulick - Austin TX
Terry G. Lawell - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H04J 304
US Classification:
370 77
Abstract:
A data link controller is provided which is suitable for use in ISDN applications, employing bit-oriented protocols. The data link controller can be operated in a time-division multiplexed mode or a non-time-division multiplexed mode. In the multiplexed mode, data in one of up to thirty-one selectable time slots is received by the data link controller under control of a microprocessor. One of the time slots can be selected via the microprocessor which allows a lengthened contiguous number of bits to be received, effectively increasing the reception rate. In the non-multiplexed mode, data is received in a continuous stream. In the multiplexed mode, up to thirty-one time slots are available for transmission of data. One of the time slots can be selected which allows a lengthened continuous number of bits to be transmitted, effectively increasing the transmission rate. In the lengthened configuration, by doubling the length of the time slot, two 64 kbps B-channels can act as a single 128 kbps channel.

Enhanced Universal Asynchronous Receiver-Transmitter

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US Patent:
49493337, Aug 14, 1990
Filed:
Nov 27, 1989
Appl. No.:
7/443088
Inventors:
Dale E. Gulick - Austin TX
Terry G. Lawell - Austin TX
Charles Crowe - Germantown TN
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H04J 1500
H04L 514
US Classification:
370 32
Abstract:
A universal asynchronous receiver-transmitter (UART) (54) is dislosed which is compatible with an industry standard yet provides additional features. The UART can be selectably operated in a synchronous or an asynchronous mode. First-in, first-out (FIFO) registers (404,424) are provided for both the receiver and transmitter portions of the UART, and a parity error and special character recognizer unit (412) on the receive side flags characters when they are placed in the reveive FIFO. Reception of a special character or one with a parity error is reported to the user via an interrupt mechanism (430). A random access memory (RAM) (413) with the special character recognized stores user-supplied patterns which are recognized as special characters. User-accessible status and control registers (408) have bit positions which enable and control the enhanced functions of the UART while maintaining compatability with the industry standard.

Data Processing System And Method Thereof

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US Patent:
57520747, May 12, 1998
Filed:
Feb 10, 1995
Appl. No.:
8/390191
Inventors:
Michael G. Gallup - Austin TX
L. Rodney Goke - Austin TX
Robert W. Seaton - Austin TX
Terry G. Lawell - Austin TX
Stephen G. Osborn - Austin TX
Thomas J. Tomazin - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1576
G06F 1580
G06F 1516
US Classification:
395800
Abstract:
A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Data Protocol Controller

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US Patent:
49072250, Mar 6, 1990
Filed:
Jun 16, 1989
Appl. No.:
7/368083
Inventors:
Dale E. Gulick - Austin TX
Terry G. Lawell - Austin TX
Charles Crowe - Germantown TN
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H04J 324
US Classification:
370 941
Abstract:
An integrated data protocol controller (IDPC)(10) is disclosed which includes on a single chip a data link controller (DLC)(52), a universal asynchronous receiver-transmitter (UART)(54) and a dual port timing controller (DPTC)(56). The IDPC is designed to support bit-oriented protocols such as is used in integrated services digital networks (ISDN). A microprocessor interface (50) on the IDPC chip permits a user to control and monitor the IDPC functions via a local microprocessor (18). The IDPC can be connected to a host processor (595) which shares a random access memory (RAM)(22a) with the local processor, allowing interprocessor communication via memory-resident buffers and mailboxes. A set of control and status registers is available within each of the main blocks of the IDPC--the DLC, the UART and the DPTC--to permit user access and control of the respective blocks. The DLC, the UART and the DPTC provide enhanced functions beyond those available in individual chips realizing a DLC, a UART or a DPTC.

Data Processing System And Method Thereof

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US Patent:
57179476, Feb 10, 1998
Filed:
Mar 31, 1993
Appl. No.:
8/040779
Inventors:
Michael G. Gallup - Austin TX
L. Rodney Goke - Austin TX
Robert W. Seaton - Austin TX
Terry G. Lawell - Austin TX
Stephen G. Osborn - Austin TX
Thomas J. Tomazin - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G06F 1580
G06F 1716
US Classification:
39580003
Abstract:
A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.
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Terry G Lawell from Austin, TX, age ~82 Get Report