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Tinghao Frank Wang

from Fremont, CA
Age ~63
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Also known as:
Tinghao F Wang, Frank T Wang, Frank Wang Tinghao, Tfrank Wang, Ting H Wang, Ho Wang Ting, Wang Ting-Hao
Related to:
Yan Lei, 34
Connected to:
Afu Wang, 80Anben Wang, 35Anke Wang, 29Anning Wang, 60Antai N Wang, 52Azhen Wang, 61Baikuan Wang, 62Baocong Wang, 33Baokun Wang, 42Baylen K Wang, 66

Tinghao Wang Phones & Addresses

  • Fremont, CA
  • 5002 Alcorn Ln, Irvine, CA 92603 (949) 856-2003 (949) 856-9797
  • Scarborough, ME
  • South Portland, ME
  • Santa Cruz, CA
  • Wappingers Falls, NY
  • 5002 Alcorn Ln, Irvine, CA 92603 (949) 856-9797

Work

Position: Sales Occupations

Education

School / High School: University of Washington 2016 to 2020

Resumes

Resumes

Tinghao Wang Photo 1

Tinghao Wang

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Education:
University of Washington 2016 - 2020

Publications

Us Patents

Method For Etching And/Or Patterning A Silicon-Containing Layer

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US Patent:
6890860, May 10, 2005
Filed:
Jun 30, 1999
Appl. No.:
09/345173
Inventors:
Tinghao F. Wang - Fremont CA, US
Usha Raghuram - San Jose CA, US
James E. Nulty - San Jose CA, US
Assignee:
Cypress Semiconductor Corporation - San Jose CA
International Classification:
H01L021/302
H01L021/461
US Classification:
438706, 438716, 438719, 438723, 438745, 438753, 438756, 134 11, 134 12, 134 13
Abstract:
Prior to etching a poly-II layer during fabrication of an integrated circuit, a hydrofluoric acid (HF) dip is used to remove surface oxides from the poly-silicon layer and an anisotropic descumming operation is used to remove any resist material left over from a patterning operation. Following patterning, a long breakthrough etch (e. g. , sufficient to remove 300-1500 Å of oxide) using an anisotropic breakthrough etchant (e. g. , a fluorocarbon-based etchant) is performed before the poly-silicon layer is etched. The HF dip may be repeated if a predetermined time between the first dip and the etch is exceeded. The anisotropic descumming operation may be performed using an anisotropic anti-reflective coating (ARC) etch, e. g. , a Cl/O, HBr/O, CF/Oor another etch having an etch rate of approximately 3000 Å/min for approximately 10-20 seconds. The poly-silicon layer may be annealed following (but not prior to) the etch thereof.

Method For Patterning Densely Packed Metal Segments In A Semiconductor Die And Related Structure

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US Patent:
6919272, Jul 19, 2005
Filed:
Feb 1, 2003
Appl. No.:
10/356447
Inventors:
Tinghao F. Wang - Irvine CA, US
Dieter Dornisch - Carlsbad CA, US
Julia M. Wu - Las Flores CA, US
Hadi Abdul-Ridha - Irvine CA, US
David J. Howard - Irvine CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L021/44
US Classification:
438669, 438671, 438712, 438720, 438942, 438945
Abstract:
A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Densely Packed Metal Segments Patterned In A Semiconductor Die

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US Patent:
7709949, May 4, 2010
Filed:
Apr 22, 2005
Appl. No.:
11/112194
Inventors:
Tinghao F. Wang - Irvine CA, US
Dieter Dornisch - Carlsbad CA, US
Julia M. Wu - Las Flores CA, US
Hadi Abdul-Ridha - Irvine CA, US
David J. Howard - Irvine CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L 23/48
US Classification:
257704, 257750, 257752, 257758, 257E21311, 257E21589
Abstract:
A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Method For Fabricating A Mim Capacitor Having Increased Capacitance Density And Related Structure

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US Patent:
7268038, Sep 11, 2007
Filed:
Nov 23, 2004
Appl. No.:
10/997638
Inventors:
Dieter Dornisch - Carlsbad CA, US
Kenneth M. Ring - Tustin CA, US
Tinghao F. Wang - Irvine CA, US
David Howard - Irvine CA, US
Guangming Li - Irvine CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L 21/8242
US Classification:
438250, 257303, 257E21351, 438240, 438396
Abstract:
According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12. 5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2. 0 fF/um.

Method For Selectively Etching Silicon And/Or Metal Silicides

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US Patent:
20020090817, Jul 11, 2002
Filed:
Feb 7, 2002
Appl. No.:
10/072082
Inventors:
Tinghao Wang - Fremont CA, US
Assignee:
Cypress Semiconductor Corporation
International Classification:
H01L021/302
H01L021/461
US Classification:
438/689000
Abstract:
A metal silicide (e.g., WSi) layer an integrated circuit is etched in a Cl/Oenvironment having an Oconcentration of greater than or equal to 25% by volume. This environment may be provided at a pressure of-approximately 2-40 mili-Torr, in a reactor with a source power of approximately 200-2000 Watts and a bias power of approximately 30-400 Watts for approximately 30 seconds. In one particular example, the Cl/Oenvironment includes approximately 45 sccm Cland 30 sccm O. The metal silicide layer is fully etched without etching an underlying poly-silicon layer. The metal silicide layer may be a portion of a gate structure.

Method For Selectively Etching Silicon And/Or Metal Silicides

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US Patent:
20020132478, Sep 19, 2002
Filed:
Jun 29, 1999
Appl. No.:
09/342335
Inventors:
TINGHAO FRANK WANG - FREMONT CA, US
International Classification:
H01L021/302
H01L021/461
US Classification:
438/689000
Abstract:
A metal silicide (e.g., WSi) layer an integrated circuit is etched in a Cl/Oenvironment having an Oconcentration of greater than or equal to 25% by volume. This environment may be provided at a pressure of approximately 2-40 mili-Torr, in a reactor with a source power of approximately 200-2000 Watts and a bias power of approximately 30-400 Watts for approximately 30 seconds. In one particular example, the Cl/Oenvironment includes approximately 45 sccm Cland sccm O. The metal silicide layer is fully etched without etching an underlying poly-silicon layer. The metal silicide layer may be a portion of a gate structure.

Method For Selectively Etching Silicon And/Or Metal Silicides

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US Patent:
20020142596, Oct 3, 2002
Filed:
Feb 7, 2002
Appl. No.:
10/071809
Inventors:
Tinghao Wang - Fremont CA, US
Assignee:
Cypress Semiconductor Corporation
International Classification:
H01L021/302
US Classification:
438/689000
Abstract:
A metal silicide (e.g., WSi) layer an integrated circuit is etched in a Cl/Oenvironment having an Oconcentration of greater than or equal to 25% by volume. This environment may be provided at a pressure of approximately 2-40 mili-Torr, in a reactor with a source power of approximately 200-2000 Watts and a bias power of approximately 30-400 Watts for approximately 30 seconds. In one particular example, the Cl/Oenvironment includes approximately 45 sccm Cland 30 sccm O. The metal silicide layer is fully etched without etching an underlying poly-silicon layer. The metal silicide layer may be a portion of a gate structure.

Pedestal Assembly For Plasma Processing Apparatus

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US Patent:
20180286639, Oct 4, 2018
Filed:
Mar 27, 2018
Appl. No.:
15/936744
Inventors:
- Fremont CA, US
Tinghao Frank Wang - Santa Cruz CA, US
International Classification:
H01J 37/32
H01L 21/67
H01L 21/683
Abstract:
Pedestal assemblies for processing apparatus, such as plasma processing apparatus are provided. In one example implementation, a plasma processing apparatus can include a processing chamber having a processing chamber interior. The apparatus can include a plasma source configured to induce a plasma in the processing chamber interior. The apparatus can include a pedestal configured to support a substrate in the processing chamber interior during processing of the substrate. The apparatus can include a focus ring configured to be disposed around a periphery of the substrate when the substrate is supported on the pedestal. The focus ring can have a plurality of uniformly spaced apart slots. Each slot can be configured to engage with a corresponding protrusion located on the pedestal.
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Tinghao Frank Wang from Fremont, CA, age ~63 Get Report