Travis R Johnson

20120312711, Dec 13, 2012

Jun 1, 2012

13/486820

Edward A. Davies - Pleasanton CA, US
Bradley Abeson - Vancouver WA, US
Travis Johnson - Vista CA, US

C09J 7/02
A61J 1/00
B32B 7/12
B32B 5/00
B29C 49/04
B32B 37/00
B65D 30/08
B31B 49/04

206438, 383107, 206525, 493267, 428347, 428220, 264510, 15624411

The present invention relates to generating a film suitable for medical packaging. The film is generated by blown film co-extrusion to form a multi-layer film which has a heat resistant layer, a barrier layer and a heat seal layer. The barrier layer includes a high barrier resin and a branched co-polymer. The high barrier resin has a density of at least 0.963 g/cm. The barrier layer includes between 25% and 85% high barrier resin. The heat resistant layer may be comprised of polymers, papers and other materials. The heat seal layer, in some embodiments, comprises any of high density polyethylene and medium density polyethylene, or a combination thereof. In some embodiments, an additional laminate layer may be affixed to the heat resistant layer of the multi-layer film. The final film is between 3.0 and 3.8 mils in thickness, and has a moisture vapor transmission rate of less than 0.08.

20220253401, Aug 11, 2022

Apr 26, 2022

17/729336

- Santa Clara CA, US
Travis Johnson - Santa Clara CA, US
Quinn Jacobson - Santa Clara CA, US
Sarma Jonnavithula - Bangalore, IN

G06F 15/78
H04W 88/08
H04L 47/41
H04L 47/30
H04L 47/722
H04L 49/351

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

20200356514, Nov 12, 2020

Apr 20, 2020

16/852967

Kent Orthner - Santa Clara CA, US
Travis Johnson - Santa Clara CA, US
Quinn Jacobson - Santa Clara CA, US
Sarma Jonnavithula - Bangalore, IN

G06F 13/40
H03K 19/17736

Methods, systems, and computer programs are presented for distributing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an iNOC comprising iNOC rows and iNOC columns; a set of clusters coupled to the iNOC, each cluster comprising a vertical network access point (NAP) for iNOC column communications, a horizontal NAP for iNOC row communications, a valid signal, and programmable logic, where the vertical NAP is connected to the horizontal NAP when the valid signal is activated; and an Ethernet controller coupled to the iNOC, the Ethernet controller configurable to send Ethernet-packet segments to the vertical NAPs.

20200356522, Nov 12, 2020

Apr 20, 2020

16/852958

Kent Orthner - Santa Clara CA, US
Travis Johnson - Santa Clara CA, US
Quinn Jacobson - Santa Clara CA, US
Sarma Jonnavithula - Bangalore, IN

G06F 15/78
H04W 88/08
H04L 12/931
H04L 12/835
H04L 12/925
H04L 12/891

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns; clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.