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Triet M Nguyen

from San Jose, CA
Age ~56
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Also known as:
Triet Minh Nguyen, Triet N Nguyen, Minh Triet Nguyen, Minh Nguyen Triet, Minh N Triet
Phone and address:
3202 Locke Dr, San Jose, CA 95111
(408) 629-1634
Related to:
Van Hien NguyenTim Tuana Nguyen, 52Thao Toan Nguyen, 63Man M Nguyen, 60Katherine T NguyenViet V Nguyen, 53Jenny L Nguyen, 52Younghee NguyenVi B Nguyen, 45Loan Le, 86John D Mero, 68N Lengoc, 49Minh N Triet, 61Tony Nguyen, 44Cheryl T NguyenHuong T Nguyen, 64Kim MeroPhuong L Nguyen, 34Binh Nguyen, 38N Thipham Nguyen
Connected to:
Aaronson Q Nguyen, 37Ai-My T Nguyen, 49Aleena D Nguyen, 35Alicia Nguyen, 39Alissa T Nguyen, 41Alysse T Nguyen, 48Andern M Nguyen, 58Andrews T Nguyen, 80Anh-Thi P Nguyen, 32Anh-Thuy Nguyen, 60

Triet Nguyen Phones & Addresses

  • 3202 Locke Dr, San Jose, CA 95111 (408) 629-1634
  • Lancaster, CA

Professional Records

Real Estate Brokers

Triet Nguyen Photo 1

Triet Nguyen, Santa Clara CA Agent

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Work:
Tera Properties
Santa Clara, CA
(408) 457-3001 (Phone)
License #01313274

Medicine Doctors

Triet Nguyen Photo 2

Triet M. Nguyen

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Specialties:
Psychiatry
Work:
UW Valley Medical Center Psychiatry & Counseling Center
4445 Talbot Rd S, Renton, WA 98055
(425) 656-4055 (phone), (425) 656-5425 (fax)
Education:
Medical School
A.T. Still University of Health Sciences/ Kirksville College of Osteopathic Medicine
Graduated: 2001
Procedures:
Psychiatric Diagnosis or Evaluation
Psychiatric Therapeutic Procedures
Conditions:
Anxiety Dissociative and Somatoform Disorders
Anxiety Phobic Disorders
Attention Deficit Disorder (ADD)
Bipolar Disorder
Depressive Disorders
Languages:
English
Spanish
Description:
Dr. Nguyen graduated from the A.T. Still University of Health Sciences/ Kirksville College of Osteopathic Medicine in 2001. He works in Renton, WA and specializes in Psychiatry. Dr. Nguyen is affiliated with UW Medicine-Valley Medical Center.
Triet Nguyen Photo 3

Triet M. Nguyen

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Specialties:
Ophthalmology
Work:
Omnivision
9286 Bolsa Ave, Westminster, CA 92683
(714) 899-0054 (phone), (714) 899-0117 (fax)
Education:
Medical School
Yale University School of Medicine
Graduated: 1989
Conditions:
Acute Conjunctivitis
Cataract
Diabetic Retinopathy
Glaucoma
Keratitis
Languages:
English
Vietnamese
Description:
Dr. Nguyen graduated from the Yale University School of Medicine in 1989. He works in Westminster, CA and specializes in Ophthalmology. Dr. Nguyen is affiliated with Newport Bay Hospital.
Triet Nguyen Photo 4

Triet S. Nguyen

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Specialties:
Family Medicine
Work:
PKA Medical Corporation
1610 W Edinger Ave STE B, Santa Ana, CA 92704
(714) 641-1610 (phone), (714) 641-1146 (fax)
Languages:
English
Spanish
Vietnamese
Description:
Ms. Nguyen works in Santa Ana, CA and specializes in Family Medicine. Ms. Nguyen is affiliated with Orange Coast Memorial Medical Center and South Coast Global Medical Center.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Triet Nguyen
President
TERA INSURANCE SERVICES, INC
Insurance Agent/Broker
2050 Concourse Dr #66, San Jose, CA 95131
1885 Lundy Ave, San Jose, CA 95131
Triet M. Nguyen
Principal
Tera Mortgage Group
Investor
1879 Lundy Ave, San Jose, CA 95131
2050 Concourse Dr, San Jose, CA 95131
Triet Nguyen
Secretary
HT PRECISION CORPORATION
Automotive Repair
2284 Trade Zone Blvd, San Jose, CA 95131
(408) 719-1826
Triet Minh Nguyen
President
COA CONSTRUCTION INC
2114 Sener Rd #16, San Jose, CA 95112
2114 Senter Rd, San Jose, CA 95112
Triet Nguyen
Principal
Nguyen Oanh Q Trinh
Business Services at Non-Commercial Site
510 Davenport Dr, San Jose, CA 95127
Triet Nguyen
MM
Vinh Long Village, LC
Triet Nguyen
MM
VINH LONG VILLAGE LLC

Publications

Us Patents

Line Segmentation In Programmable Logic Devices Having Redundancy Circuitry

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US Patent:
6759871, Jul 6, 2004
Filed:
Apr 22, 2003
Appl. No.:
10/422007
Inventors:
Triet Nguyen - San Jose CA
Changsong Zhang - San Jose CA
David Jefferson - Morgan Hill CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K 19177
US Classification:
326 41, 326 38, 326 82
Abstract:
Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.

Flexible I/O Routing Resources

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US Patent:
6826741, Nov 30, 2004
Filed:
Nov 6, 2002
Appl. No.:
10/289629
Inventors:
Brian D. Johnson - Sunnyvale CA
Andy L. Lee - San Jose CA
Cameron McClintock - Mountain View CA
Triet Nguyen - San Jose CA
David Jefferson - Morgan Hill CA
Paul Leventis - Toronto, CA
David Lewis - Toronto, CA
Vaughn Betz - Toronto, CA
Michael Chan - Scarborough, CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 1750
US Classification:
716 12, 716 16, 716 17
Abstract:
In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.

Programmable Logic Device With Redundant Circuitry

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US Patent:
6965249, Nov 15, 2005
Filed:
May 30, 2002
Appl. No.:
10/159581
Inventors:
Christopher Lane - San Jose CA, US
Ketan Zaveri - San Jose CA, US
Hyun Yi - San Jose CA, US
Giles Powell - Alameda CA, US
Paul Leventis - Ontario, CA
David Jefferson - Morgan Hill CA, US
David Lewis - Ontario, CA
Triet Nguyen - San Jose CA, US
Vikram Santurkar - San Jose CA, US
Michael Chan - Ontario, CA
Andy Lee - San Jose CA, US
Brian Johnson - Sunnyvale CA, US
David Cashman - Ontario, CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
H03K019/177
US Classification:
326 10, 326 9, 326 41
Abstract:
A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.

Programmable Clock Network For Distributing Clock Signals To And Between First And Second Sections Of An Integrated Circuit

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US Patent:
6996736, Feb 7, 2006
Filed:
Feb 12, 2002
Appl. No.:
10/076172
Inventors:
Triet Nguyen - San Jose CA, US
David Jefferson - Morgan Hill CA, US
Srinivas Reddy - Fremont CA, US
Keone Streicher - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 1/10
US Classification:
713500, 326 39, 326 93
Abstract:
A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.

Programmable Clock Network For Distributing Clock Signals To And Between First And Second Sections Of An Integrated Circuit

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US Patent:
7228451, Jun 5, 2007
Filed:
Nov 8, 2005
Appl. No.:
11/270801
Inventors:
Triet Nguyen - San Jose CA, US
David Jefferson - Morgan Hill CA, US
Srinivas Reddy - Fremont CA, US
Keone Streicher - San Jose CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 1/04
US Classification:
713500, 713503, 326 39
Abstract:
A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.

Adder-Rounder Circuitry For Specialized Processing Block In Programmable Logic Device

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US Patent:
7822799, Oct 26, 2010
Filed:
Jun 26, 2006
Appl. No.:
11/426403
Inventors:
Martin Langhammer - Alderbury, GB
Triet M. Nguyen - San Jose CA, US
Yi-Wen Lin - Pasadena CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 7/38
US Classification:
708551, 708709
Abstract:
Adder/rounder circuitry for use in a programmable logic device computes a rounded sum quickly, and ideally within one clock cycle. The rounding position is selectable within a range of bit positions. In an input stage, for each bit position in that range, bits from both addends and a rounding bit are processed, while for each bit position outside that range only bits from both addends are processed. The input stage processing aligns its output in a common format for bits within and outside the range. The input processing may include 3:2 compression for bit positions within the range and 2:2 compression for bit positions outside the range, so that further processing is performed for all bit positions on a sum vector and a carry vector. Computation of the sum proceeds substantially simultaneously with and without the rounding input, and rounding logic makes a selection later in the computation.

Specialized Processing Block For Programmable Logic Device

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US Patent:
7836117, Nov 16, 2010
Filed:
Jul 18, 2006
Appl. No.:
11/458361
Inventors:
Martin Langhammer - Salisbury, GB
Kwan Yee Martin Lee - Hayward CA, US
Triet M. Nguyen - San Jose CA, US
Keone Streicher - San Ramon CA, US
Orang Azgomi - Sunnyvale CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 7/38
US Classification:
708603
Abstract:
A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less area than conventional separate multipliers and adders. The specialized processing block further has input and output stages, as well as a loopback function, to allow the block to be configured for various digital signal processing operations.

Memory Elements With Leakage Compensation

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US Patent:
7864603, Jan 4, 2011
Filed:
Feb 26, 2008
Appl. No.:
12/037911
Inventors:
John Henry Bui - Sunnyvale CA, US
Triet M. Nguyen - San Jose CA, US
David E. Jefferson - Morgan Hill CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G11C 7/18
US Classification:
36518919, 36518911, 365203, 36518905, 36523001, 36518915
Abstract:
Integrated circuits with memory elements are provided. The memory elements may be arranged in an array. Data lines may be used to load data into the memory elements and may be used to read data from the memory elements. The memory elements may be used to store configuration data on a programmable logic device integrated circuit. Each memory element may have an output that supplies a programmable transistor gate with a static control signal. Data reading circuitry may be coupled to each data line to read data from an addressed memory element on that data line. The data reading circuitry for each data line may include a precharge transistor and an output latch. The output latch may contain cross-coupled inverters. An inwardly-directed inverter in the output latch may have a pull-up transistor that is connected in series with a current source.

Amazon

Investing in the High Yield Municipal Market: How to Profit from the Current Municipal Credit Crisis and Earn Attractive Tax-Exempt Interest Income

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A practical guide to profiting from the high yield municipal market This unique guide to the high yield municipal bond market sheds some much-needed light on this esoteric but profitable corner of the fixed-income world. It fills the void between the general reference handbooks on municipal bonds an...
Author

Triet Nguyen

Binding

Hardcover

Pages

264

Publisher

Wiley

ISBN #

1118175476

EAN Code

9781118175477

ISBN #

1

Investing in the High Yield Municipal Market: How to Profit from the Current Municipal Credit Crisis and Earn Attractive Tax-Exempt Interest Income (Bloomberg Financial) [Hardcover] [2012] (Author) Triet Nguyen

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Binding

Hardcover

Publisher

Wiley

ISBN #

2

Investing in the High Yield Municipal Market How to Profit from the Current Municipal Credit Crisis and Earn Attractive Tax-Exempt Interest Income [Bloomberg Financial] by Nguyen, Triet [Wiley,2012] [Hardcover]

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Investing in the High Yield Municipal Market How to Profit from the Current M.... Wiley, 2012.
Binding

Hardcover

Publisher

Wiley,2012

ISBN #

4

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Triet M Nguyen from San Jose, CA, age ~56 Get Report