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Ajit K Trivedi

from Endicott, NY
Deceased
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Also known as:
Ajitk Trivedi
Phone and address:
4 Newberry Dr, Endicott, NY 13760
(607) 754-3543
Related to:
Christina A Willis, 36Bhavya Trivedi, 51Doris Strickland, 75
Connected to:
Akshata Trivedi, 32Amita R Trivedi, 47Amruta M Trivedi, 32Anshuman Trivedi, 36Bindumathi K Trivedi, 49Coral B Trivedi, 34Devalkumari N Trivedi, 47Devang B Trivedi, 61Dharmesh J Trivedi, 58Dhiren M Trivedi, 52

Ajit Trivedi Phones & Addresses

  • 4 Newberry Dr, Endicott, NY 13760 (607) 754-3543
  • Chicago, IL
  • 4 Newberry Dr, Endicott, NY 13760

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: Associate degree or higher

Emails

d***[email protected]

Publications

Us Patents

Proper Choice Of The Encapsulant Volumetric Cte For Different Pgba Substrates

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US Patent:
6353182, Mar 5, 2002
Filed:
Mar 30, 1998
Appl. No.:
09/050765
Inventors:
Chi Shih Chang - Austin TX
William T. Chen - Endicott NY
Ajit Trivedi - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2328
US Classification:
174 522, 174 523, 174 524, 174255, 174260, 257632, 257678, 257701, 257737, 257738, 361748, 361767
Abstract:
The present invention describes a method and apparatus for packaging a flip chip by matching the z-direction CTE of the IC solder joint with the z-direction CTE of the encapsulant. Consideration of the z-direction CTEs is important when determining the volumetric CTE of the encapsulant. This invention first requires a determination of the z-direction CTE of the IC solder joint and a determination of the z-direction CTE of the encapsulant. The invention next matches the z-direction CTE of the IC solder joint to the z-direction CTE of the encapsulant. The matching of the two z-direction CTEs reduces the z-direction tensile or compression stresses on the IC solder joint and the encapsulant.

Apparatus And Method For Printed Circuit Board Repair

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US Patent:
6437254, Aug 20, 2002
Filed:
Aug 24, 2001
Appl. No.:
09/938402
Inventors:
Alan Harris Crudo - Endicott NY
John Gillette Davis - Charlotte NC
Christian Robert Le Coz - Endicott NY
Mark Vincent Pierson - Binghamton NY
Amit Kumar Sarkhel - Endicott NY
Ajit Kumar Trivedi - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01R 909
US Classification:
174267, 361803, 439 46, 439591, 324758
Abstract:
A method and apparatus for efficiently repairing or reworking a printed circuit board having a solder ball grid array thereon efficiently and at minimum cost includes the steps of drilling out a plated-through hole to sever electrical connections between a ball grid array pad on one surface of the printed circuit board and internal circuits and circuits on an opposite surface of the printed circuit board; inserting a pin having an insulated sleeve surrounding a portion thereof into the drilled-out hole, the pin having attached to one end a wire for attachment to the ball grid array on one surface of the printed circuit board and a post at the other end of the pin for attachment of a wire to the post; the pin having a stop along its length to control vertical positioning of the pin in the drilled-out hole, the pin referred to as a via replacement (VR) pin. Alternately, after the plated through hole is drilled out, an insulated wire may be inserted into the hole with insulation removed from the length of the wire which extends beyond one surface of the printed circuit board. The bare length of wire is bent parallel to the surface of the printed circuit board and attached thereto by a solder reflow process.

Cooling Method For Electronic Components

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US Patent:
6453537, Sep 24, 2002
Filed:
Nov 10, 1999
Appl. No.:
09/431751
Inventors:
Craig G. Heim - Kirkwood NY
Wade Leslie Hooker - Endicott NY
Ajit Kumar Trivedi - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
B23P 1902
US Classification:
294264, 29739, 294261, 29832, 294028, 228119, 228264, 257715, 361719, 361700, 16510421, 165185, 174 163, 174252
Abstract:
A method for cooling electrical components on a substrate during a rework process. A block of a porous, thermally conductive material, saturated with a liquid, is positioned on an electrical component to be cooled. During the rework processing of an adjacent electrical component, the liquid in the porous, thermally conductive block vaporizes, thereby maintaining the temperature of the electrical component below its reflow temperature. A second thermally conductive block, in thermal contact with the porous, thermally conductive block, and the substrate on which the electronic component to be cooled is attached, is positioned between the electronic component to be cooled and the electronic component undergoing rework. A supply of liquid is provided to the porous, thermally conductive block to maintain the temperature of the electronic component to be cooled at a predetermined level for a specified period of time.

Wafer Scale Encapsulation For Integrated Flip Chip And Surface Mount Technology Assembly

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US Patent:
6492071, Dec 10, 2002
Filed:
Sep 26, 2000
Appl. No.:
09/670410
Inventors:
William E. Bernier - Endwell NY
Mark V. Pierson - Binghamton NY
Ajit K. Trivedi - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G03F 900
US Classification:
430 5, 430308, 438106, 438108, 438112, 438114
Abstract:
A device and process for applying mixtures of adhesive formulations combined with solder flux such that flip chips may be rapidly encapsulated with such combinations without interfering with subsequent wafer processing steps are provided. Also provided is a wafer stencil designed in such a manner that the saw kerf lines separating individual chip dies are protected from coming into contact with the formulation. Extrusion screening using such wafer stencil is also provided.

Method And Device For Semiconductor Testing Using Electrically Conductive Adhesives

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US Patent:
6559666, May 6, 2003
Filed:
Jun 6, 2001
Appl. No.:
09/875246
Inventors:
William E. Bernier - Endwell NY
Michael A. Gaynes - Vestal NY
Wayne J. Howell - Williston VT
Mark V. Pierson - Binghamton NY
Ajit K. Trivedi - Endwell NY
Charles G. Woychik - Vestal NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 3102
US Classification:
324755, 324765
Abstract:
A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.

Low Or No-Force Bump Flattening Structure And Method

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US Patent:
6674647, Jan 6, 2004
Filed:
Jan 7, 2002
Appl. No.:
10/040740
Inventors:
Mark V. Pierson - Binghamton NY
Ajit K. Trivedi - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 710
US Classification:
361760, 361772, 257692, 257738
Abstract:
Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.

Placement Of Sacrificial Solder Balls Underneath The Pbga Substrate

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US Patent:
6829149, Dec 7, 2004
Filed:
Aug 18, 1997
Appl. No.:
08/912429
Inventors:
Chi Shih Chang - Austin TX
William T. Chen - Endicott NY
Ajit Trivedi - Endicott NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H05K 712
US Classification:
361771, 361704, 361707, 361712, 361714
Abstract:
The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.

Placement Of Sacrificial Solder Balls Underneath The Pbga Substrate

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US Patent:
7227268, Jun 5, 2007
Filed:
Oct 29, 2004
Appl. No.:
10/977263
Inventors:
Chi Shih Chang - Austin TX, US
William T. Chen - Endicott NY, US
Ajit Trivedi - Endicott NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 23/48
H01L 23/52
H01L 29/40
US Classification:
257786, 257738, 257778, 257E2302, 257E23021, 257E23023, 257E23069, 438108, 438109
Abstract:
The present invention discloses techniques that improve the reliability of a flip packages that uses underfill encapsulation. One embodiment of the present invention describes a method and apparatus of packaging a flip chip by relocating the neutral plane of the package substrate away from its mid-plane. Another embodiment of the present invention describes a method and apparatus of arranging the layers of a laminate for use in PBGA packaging that arranges the layers of the laminate according to the stiffness of each layer. Another embodiment of the present invention describes a method and apparatus of packaging a flip chip that uses one or more redundant interconnections at the bottom of the package substrate where the redundant interconnections are within the shadow of the IC chip.
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Ajit K Trivedi from Endicott, NYDeceased Get Report