Ajith Kurian Issac

Colorado Springs, CO

Semiconductors

Intel Corporation Oct 2013 - Oct 2014
Senior Vlsi Design Engineer
Broadcom Oct 2013 - Oct 2014
Ic Design Engineer
Wipro Technologies Jan 2008 - Feb 2013
Vlsi Design Engineer
Texas Instruments Mar 2012 - Dec 2012
Senior Vlsi Design Engineer

Birla Institute of Technology and Science, Pilani 2010 - 2012
Master of Science, Masters Ilahia College of Engineering 2003 - 2007
Bachelors, Bachelor of Technology Sndp Higher Secondary School, Muvattupuzha
Fathima Matha English Medium High School, Piravom
Ilahia College of Engineering and Technology, Muvattupuzha

Asic
Vlsi
Verilog
Soc
Logic Synthesis
Tcl
Vhdl
Microcontrollers
Rtl Design
Perl
Assertion Based Verification
Verification
Formal Verification
Ic
Functional Verification
Systemverilog
Ncsim
Static Timing Analysis
Physical Design
Application Specific Integrated Circuits
Module
Primetime
Arm
Low Power Design
Modelsim
Timing Closure
Integrated Circuit Design
Very Large Scale Integration
Silicon Validation
Statistical Tools
Jtag
Dft
Processors
Veritas Cluster Server
Power Analysis
Rtl Coding
Open Verification Methodology
Perl and Tcl Scripting
Tool Development
Methodology Development
Jtag and Debug Related Module Verification
Post Silicon Validation
Synthesis
Dual Core Cpu Integration
Asm Based Soc Verification
Power Analyss
Soc Integration and Design

Tool Devlopment
Blogging
Scripting

English
Malayalam
Hindi