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Alin T Iacob

from Sunnyvale, CA
Age ~60
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Also known as:
Alin Teodor Iacob, Teodor Alin Iacob, Teodor T Iacob, Teodor A Iacob, Teodora Alin Iacob, Alin Teodor Jacob, Theodor A Iacob, Iacob Alin, Theadore Iacob
Phone and address:
1462 Yukon Dr, Sunnyvale, CA 94087
(408) 616-8978
Related to:
Melissa M Michaud, 42Simon Iacob, 35Stela Iacob, 58Stela Jacob, 58Roy Iacob, 31
Connected to:
Sylvianne Iacobaccio, 75Rodica Iacoban, 62Ionela Iacobas, 47Diona A Iacobazzi, 47Corinne S Iacobellis, 82Elizabeth A Iacobelli, 64Elva Iacobelli, 97Greg Iacobelli, 55Lanette A Iacobelli, 51Lizabeth Iacobelli, 72

Alin Iacob Phones & Addresses

  • 1462 Yukon Dr, Sunnyvale, CA 94087 (408) 616-8978
  • 1074 Knickerbocker Dr, Sunnyvale, CA 94087 (408) 616-8978
  • Gayville, SD
  • Santa Clara, CA

Emails

t***[email protected]

Resumes

Resumes

Alin Iacob Photo 1

Senior Software Engineer At Oce/Canon

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Position:
Senior Software Engineer at Oce/Canon
Location:
Timis County, Romania
Industry:
Computer Software
Work:
Oce/Canon - Timisoara since Feb 2008
Senior Software Engineer
S.C Sarmet S.R.L. Oct 2007 - Feb 2008
Software Developer
Education:
Universitatea „Politehnica” din Timișoara 2009 - 2011
Master's degree, Computer Science Universitatea „Politehnica” din Timișoara 2005 - 2009
Bachelor's degree, Computer Science Universitatea „Politehnica” din Timișoara 2005 - 2009
Department for Teaching Staff Training, Teaching National College `Ionita Asan` 2001 - 2005
High School Diploma, Matematics-Informatics
Skills:
OOP
C#
Design Patterns
WCF
.NET
LINQ
WPF
Silverlight
TFS
ASP.NET
ADO.NET
Software Design
Object Oriented Design
Interests:
career opportunities, business deals, reference requests, getting back in touch
Honor & Awards:
- Microsoft Excite Challenge – 1st place (16 dec 2007) ( Creating an online travel agency – asp.net/c#/sql server)
Alin Iacob Photo 2

Software Developer At Oce

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Position:
Software Developer at Oce
Location:
Timis County, Romania
Industry:
Computer Software
Work:
Oce
Software Developer
Alin Iacob Photo 3

Senior Software Engineer At Oce/Canon

View page
Position:
Senior Software Engineer at Oce/Canon
Location:
Timis County, Romania
Industry:
Computer Software
Work:
Oce/Canon - Timisoara since Feb 2008
Senior Software Engineer
S.C Sarmet S.R.L. Oct 2007 - Feb 2008
Software Developer
Education:
Universitatea „Politehnica” din Timișoara 2009 - 2011
Master's degree, Computer Science Universitatea „Politehnica” din Timișoara 2005 - 2009
Bachelor's degree, Computer Science Universitatea „Politehnica” din Timișoara 2005 - 2009
Department for Teaching Staff Training, Teaching National College `Ionita Asan` 2001 - 2005
High School Diploma, Matematics-Informatics
Skills:
OOP
C#
Design Patterns
WCF
.NET
LINQ
WPF
Silverlight
TFS
ASP.NET
ADO.NET
Interests:
career opportunities, business deals, reference requests, getting back in touch
Honor & Awards:
- Microsoft Excite Challenge – 1st place (16 dec 2007) ( Creating an online travel agency – asp.net/c#/sql server)

Publications

Us Patents

System And Method For Detecting When An External Load Is Coupled To A Video Digital-To-Analog Converter

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US Patent:
6940440, Sep 6, 2005
Filed:
Oct 24, 2003
Appl. No.:
10/692498
Inventors:
Alin Theodor Iacob - Sunnyvale CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03M001/66
US Classification:
341144
Abstract:
A system and method for determining when an external load is coupled to a digital-to-analog converter (DAC). Specifically, in one embodiment, a load detector circuit comprises a video DAC, an output circuit, a dumping circuit, and a determining circuit. The video DAC comprises a differential architecture including a first output and a second output working in opposite phase. The first DAC output is coupled to the output circuit, which drives the external load. The second DAC output is coupled to a dumping circuit, and is configured such that the dumping circuit is balanced with the output circuit when the external load is present. A determining circuit examines the two outputs of the DAC to determine if the dumping circuit is balanced with the output circuit, and thus if the external load is present.

Wafer With Saw Street Guide

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US Patent:
6972444, Dec 6, 2005
Filed:
Aug 6, 2003
Appl. No.:
10/635363
Inventors:
Alin Theodor Iacob - Sunnyvale CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L027/10
US Classification:
257202, 257203, 257208, 257209, 257210, 257266
Abstract:
A wafer is formed with metal traces that extend a distance across the wafer on opposite sides of a saw street. The resistances of the metal traces, which can each be formed from one or more layers of metal, are measured before the saw street is cut. During and after the saw street is cut, the resistances of the metal traces are again measured, even continuously. The pre-cut, during-cut, and post-cut resistances are compared to determine if the wafer has been cut without damage to the wafer due to misalignment or a worn cutting device.

System And Method For A Data-Input Array Capable Of Being Scanned Using A Reduced Number Of Signals

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US Patent:
7123170, Oct 17, 2006
Filed:
Aug 26, 2003
Appl. No.:
10/649173
Inventors:
Alin Theodor Iacob - Sunnyvale CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03M 11/00
US Classification:
341 26, 341 20, 345168
Abstract:
A system and method for scanning a data-input array (e. g. , a keyboard or keypad) using a reduced number of signals is disclosed. Specifically, a switch array is disclosed comprising a plurality of switches and a plurality of input/output (I/O) lines. The switch array is arranged in an N*N matrix. A plurality of N I/O lines is used to scan the matrix. In one embodiment, the switches in the array are arranged in an N*(N−1)/2 configuration. In this configuration, there is no duplication of circuit paths. In another embodiment, the switches in the array are arranged in an N(N−1) configuration. In this configuration, a plurality of diodes are used to identify an activated switch depending upon which of a plurality of signal paths is activated. The plurality of diodes is included to differentiate between pairs of switches that complete the same paths between pairs of I/O lines.

Apparatus And Method For Testing Power And Ground Pins On A Semiconductor Integrated Circuit

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US Patent:
7279921, Oct 9, 2007
Filed:
Jun 8, 2005
Appl. No.:
11/148465
Inventors:
Alin Theodor Iacob - Sunnyvale CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G01R 31/26
G01R 31/02
US Classification:
324765, 324537
Abstract:
To achieve the foregoing, and in accordance with the purpose of the present invention, a method and apparatus for testing individual power and ground pins on a semiconductor integrated circuit are disclosed. The method and apparatus includes organizing the power pins of the die into a first group of power pins and a second group of power pins. Each of the first group of power pins are then connected through a first set of resistors to a first common node, and each of the second group of power pins through a second set of resistors to a second common node respectively. A voltage is next applied between the first and second nodes. The voltage at each of the first group of pins is compared with a first threshold voltage and the voltage at each of the second group of pins is compared with a second threshold voltage. Individual bad pins in the first and second groups are identified based on the comparison.

Wafer Dicing System

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US Patent:
7388385, Jun 17, 2008
Filed:
Oct 19, 2005
Appl. No.:
11/253466
Inventors:
Alin Theodor Iacob - Sunnyvale CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G01R 27/08
US Classification:
324691, 257 48, 2960309
Abstract:
A wafer is formed with metal traces that extend a distance across the wafer on opposite sides of a saw street. The resistances of the metal traces, which can each be formed from one or more layers of metal, are measured before the saw street is cut. During and after the saw street is cut, the resistances of the metal traces are again measured, even continuously. The pre-cut, during-cut, and post-cut resistances are compared to determine if the wafer has been cut without damage to the wafer due to misalignment or a worn cutting device.

Power Circuit For Generating Non-Isolated Low Voltage Power In A Standby Condition

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US Patent:
7602158, Oct 13, 2009
Filed:
Mar 21, 2005
Appl. No.:
11/086215
Inventors:
Alin Theodor Iacob - Sunnyvale CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H02M 7/06
US Classification:
323231, 363126, 307 17
Abstract:
A power circuit generating a non-isolating low voltage power supply using a capacitive AC voltage drop in standby. Specifically, the power circuit includes an AC connector that generates a first AC input and a second AC input that are opposite in phase. The power circuit also includes first and second diode bridge rectifier circuits that are coupled to the first AC input, the second AC input, and a ground. A first capacitor drops a voltage of the first AC input, and a second capacitor drops a voltage of the second AC input. The first diode bridge rectifier circuit provides a high voltage power signal to a load. The second diode bridge rectifier circuit provides a low voltage power signal to a microcontroller.

Method And Apparatus For Supplying Power For A Vacuum Fluorescent Display (Vfd) Filament

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US Patent:
6531825, Mar 11, 2003
Filed:
Jul 2, 2001
Appl. No.:
09/899406
Inventors:
Alin Theodor Iacob - Sunnyvale CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H05B 4114
US Classification:
315105, 3151691, 3151694, 345 751
Abstract:
A VFD driver circuit includes a DC power supply coupled to cascaded first power operational amplifier (POA ) and second power operational amplifier (POA ). The POA is a self-oscillating power operational amplifier having a feedback circuit associated therewith whereas the POA is configured in an essentially inverting unity gain mode. The POA has a first POA output node coupled to a first terminal of a VFD filament and a second POA output node coupled to a first POA input node. The POA has a POA output node coupled to a second terminal of the VFD filament. The shape of the output waveform delivered by the POA is dependent upon the feedback circuit and can be any shape deemed suitable. Such shapes include a square wave, a sinusoidal wave, a triangular wave, a trapezoidal wave, clipped sinusoidal wave, and so on.

Grounded Ferrite In Wireless Power Systems

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US Patent:
20230103141, Mar 30, 2023
Filed:
Dec 6, 2022
Appl. No.:
18/075727
Inventors:
- CUPERTINO CA, US
Alin Theodor Iacob - Sunnyvale CA, US
Assignee:
APPLE INC. - CUPERTINO CA
International Classification:
H01F 27/24
H01F 38/14
H01F 27/36
H01F 27/28
Abstract:
Charging devices according to embodiments of the present technology may include a housing including an input configured to receive power from a power source and provide power to internal components of the charging device. The charging devices may include a ferrite. The ferrite may be coupled with electrical ground. The charging devices may also include a conductive coil seated in the ferrite. The conductive coil may be configured to generate an electromagnetic field from an AC signal.
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Alin T Iacob from Sunnyvale, CA, age ~60 Get Report