Search

Andrew Oishei Phones & Addresses

  • 11405 Nawa Way, San Diego, CA 92129 (858) 672-9268
  • Nawa Way, San Diego, CA 92129
  • 3410 Waco St, San Diego, CA 92117 (858) 275-1096 (619) 275-1096

Industries

Semiconductors

Resumes

Resumes

Andrew Oishei Photo 1

An Engineer At Altera

View page
Location:
Greater San Diego Area
Industry:
Semiconductors

Publications

Us Patents

Capacitive Decoupling Method And Module

View page
US Patent:
8332790, Dec 11, 2012
Filed:
Sep 9, 2010
Appl. No.:
12/878940
Inventors:
Andrew E. Oishei - San Diego CA, US
Gregory Moore - San Diego CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 17/50
US Classification:
716111, 716106, 716115, 703 16
Abstract:
The present invention is directed to a capacitive decoupling module and method for an integrated circuit that features providing multiple capacitive elements to decouple the power rails from the integrated circuit. The multiple capacitive elements are spaced-apart, along a first direction, from the integrated circuit. A first set of capacitive elements is closer to the integrated circuit than a second set of capacitive elements. The first set has a smaller capacitance than the second set.

Method And Apparatus For Performing Automatic Decoupling Capacitor Selection For Power Distribution Networks

View page
US Patent:
8627261, Jan 7, 2014
Filed:
Sep 14, 2011
Appl. No.:
13/232281
Inventors:
Andrew E. Oishei - San Diego CA, US
Dmitry Denisenko - Toronto, CA
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 9/455
G06F 17/50
US Classification:
716133, 716132
Abstract:
A method for designing a power distribution network (PDN) for a system implementing a target device includes computing a target PDN impedance value for the PDN. For each switching frequency of the target device where an effective PDN impedance value for the PDN is greater than the target PDN impedance value, one or more decoupling capacitors for one or more capacitor types are identified to add to the PDN to drive the effective PDN impedance value below the target PDN value. A selection of decoupling capacitors identified is refined to reduce one or more of a cost of the PDN and space required for implementing the PDN.

Capacitive Decoupling Method And Module

View page
US Patent:
7818704, Oct 19, 2010
Filed:
May 16, 2007
Appl. No.:
11/749423
Inventors:
Andrew E. Oishei - San Diego CA, US
Gregory Moore - San Diego CA, US
Assignee:
Altera Corporation - San Jose CA
International Classification:
G06F 17/50
H05K 7/02
H03K 19/0175
H03K 17/16
H01L 25/00
US Classification:
716 13, 716 14, 716 9, 716 10, 361734, 326 31, 326 88, 326 92, 326101, 327379
Abstract:
The present invention is directed to a capacitive decoupling module and method for an integrated circuit that features providing multiple capacitive elements to decouple the power rails from the integrated circuit. The multiple capacitive elements are spaced-apart, along a first direction, from the integrated circuit. A first set of capacitive elements is closer to the integrated circuit than a second set of capacitive elements. The first set has a smaller capacitance than the second set.
Andrew Eugene Oishei from San Diego, CA, age ~58 Get Report