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Anhdung Duong Ngo

from Austin, TX
Age ~53

Anhdung Ngo Phones & Addresses

  • 8903 Marybank Dr, Austin, TX 78750 (512) 773-3317
  • 15823 Hamden Cir, Austin, TX 78717 (512) 244-7380
  • 8524 Burnet Rd, Austin, TX 78757 (512) 459-8001
  • Pflugerville, TX
  • Round Rock, TX
  • Houston, TX
  • 8903 Marybank Dr, Austin, TX 78750 (512) 244-7380

Work

Company: Sifive Jan 2020 Position: Performance architect

Education

Degree: Masters School / High School: The University of Texas at Austin 1989 to 1996

Skills

Software Development • Microprocessor Performance Modeling • Microprocessor Performance Analysis • C++ • C • Software Engineering • Perl • Software Design • Oop • Application Development • Microprocessors • Computer Architecture • Embedded Systems

Industries

Semiconductors

Resumes

Resumes

Anhdung Ngo Photo 1

Performance Architect

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Sifive
Performance Architect

Freescale Semiconductor Jul 1997 - Apr 2012
System and Architecture Engineer

Samsung Austin R&D Center Jul 1997 - Apr 2012
Senior Staff Engineer

The University of Texas at Austin Sep 1994 - Jul 1997
Applied Research Laboratories
Education:
The University of Texas at Austin 1989 - 1996
Masters
Skills:
Software Development
Microprocessor Performance Modeling
Microprocessor Performance Analysis
C++
C
Software Engineering
Perl
Software Design
Oop
Application Development
Microprocessors
Computer Architecture
Embedded Systems

Publications

Us Patents

Pseudo Least Recently Used (Plru) Cache Replacement

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US Patent:
20090113137, Apr 30, 2009
Filed:
Oct 30, 2007
Appl. No.:
11/929180
Inventors:
Brian C. Grayson - Austin TX, US
Klas M. Bruce - Leander TX, US
Anhdung D. Ngo - Austin TX, US
Michael D. Snyder - Cedar Park TX, US
International Classification:
G06F 12/08
US Classification:
711136, 711E12022
Abstract:
A multi-way cache system includes multi-way cache storage circuitry, a pseudo least recently used (PLRU) tree state representative of a PLRU tree, the PLRU tree having a plurality of levels, and PLRU control circuitry coupled to the multi-way cache storage circuitry and the PLRU tree state. The PLRU control circuitry has programmable PLRU tree level update enable circuitry which selects Y levels of the plurality of levels of the PLRU tree to be updated. The PLRU control circuitry, in response to an address hitting or resulting in an allocation in the multi-way cache storage circuitry, updates only the selected Y levels of the PLRU tree state.

Branch Prediction Throughput By Skipping Over Cachelines Without Branches

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US Patent:
20200371811, Nov 26, 2020
Filed:
Sep 4, 2019
Appl. No.:
16/561004
Inventors:
- Suwon-si, KR
Fuzhou ZOU - Austin TX, US
Anhdung NGO - Austin TX, US
Wichaya Top CHANGWATCHAI - Austin TX, US
Monika TKACZYK - Austin TX, US
International Classification:
G06F 9/38
G06F 9/48
Abstract:
According to one general aspect, an apparatus may include a branch prediction circuit configured to predict if a branch instruction will be taken or not. The apparatus may include a branch target buffer circuit configured to store a memory segment empty flag that indicates whether or not the memory segment after a target address includes at least one other branch instruction, wherein the memory segment empty flag was created during a commit stage of a prior occurrence of the branch instruction. The branch prediction circuit may be configured to skip over the memory segment if the memory segment empty flag indicates a lack of other branch instruction(s).
Anhdung Duong Ngo from Austin, TX, age ~53 Get Report