Search

Anupama Suryanarayanan

from Paramus, NJ
Age ~38
Get Report
Related to:
Deepa Suryanarayanan, 46Vandhana Suryanarayanan, 43Deepa Suryanarayana, 83Poornima Suryanarayanan, 36Vishwas SuryanarayananNirupama Suryanarayanan, 40
Connected to:
Dev Suryanarayana, 58Krishna B Suryanarayana, 55Prashant Suryanarayan, 45Suresh Suryanarayanaiah, 43Trifonia Suryana, 57Winston Suryana, 36Santosh K Suryapeta, 46Hilda Suryaputra, 75Akshara Suryavanshi, 42Deepali Suryavanshi, 42

Anupama Suryanarayanan Phones & Addresses

  • Paramus, NJ
  • San Jose, CA
  • Beaverton, OR
  • 5 Parker Ave, Rochelle Park, NJ 07662
  • Pittsburgh, PA

Industries

Computer-Hardware

Resumes

Resumes

Anupama Suryanarayanan Photo 1

Student At Carnegie Mellon University

View page
Location:
Groraum Pittsburgh und Umgebung
Industry:
Computer-Hardware

Publications

Us Patents

Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Detecting And Controlling Current Ramps In Processing Circuit

View page
US Patent:
20120221871, Aug 30, 2012
Filed:
Dec 29, 2011
Appl. No.:
13/340511
Inventors:
Anupama Suryanarayanan - Hillsboro OR, US
Matthew C. Merten - Hillsboro OR, US
Ryan L. Carlson - Hillsboro OR, US
Stephen H. Gunther - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/32
US Classification:
713320
Abstract:
Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

Processor To Pre-Empt Voltage Ramps For Exit Latency Reductions

View page
US Patent:
20200042065, Feb 6, 2020
Filed:
Aug 19, 2019
Appl. No.:
16/544010
Inventors:
- Santa Clara CA, US
Jeremy J. Shrall - Portland OR, US
Anupama Suryanarayanan - Hillsboro OR, US
Ameya Ambardekar - Hillsboro OR, US
Craig Topper - Beaverton OR, US
Eric R. Heit - Hillsboro OR, US
Joseph M. Alberts - Hillsboro OR, US
International Classification:
G06F 1/28
G06F 12/0897
G06F 12/0875
G06F 12/084
G06F 1/30
G06F 1/3296
Abstract:
In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.

Computing System And Processor With Fast Power Surge Detection And Instruction Throttle Down To Provide For Low Cost Power Supply Unit

View page
US Patent:
20180232024, Aug 16, 2018
Filed:
Dec 18, 2017
Appl. No.:
15/846161
Inventors:
- Santa Clara CA, US
Martin Rowland - Beaverton OR, US
Efraim Rotem - Haifa, IL
Brian J. Griffith - Auburn WA, US
Ankush Varma - Hillsboro OR, US
Anupama Suryanarayanan - Hillsboro OR, US
International Classification:
G06F 1/26
G06F 1/32
Abstract:
A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.

Processor To Pre-Empt Voltage Ramps For Exit Latency Reductions

View page
US Patent:
20180060085, Mar 1, 2018
Filed:
Aug 31, 2016
Appl. No.:
15/252529
Inventors:
Avinash N. Ananthakrishnan - Portland OR, US
Jeremy J. Shrall - Portland OR, US
Anupama Suryanarayanan - Hillsboro OR, US
Ameya Ambardekar - Hillsboro OR, US
Craig Topper - Beaverton OR, US
Eric R. Heit - Hillsboro OR, US
Joseph M. Alberts - Hillsboro OR, US
International Classification:
G06F 9/44
G06F 12/0897
G06F 12/0875
G06F 12/084
G06F 12/0842
G06F 1/28
Abstract:
In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.

Method And Apparatus To Prevent Voltage Droop In A Computer

View page
US Patent:
20150378412, Dec 31, 2015
Filed:
Jun 30, 2014
Appl. No.:
14/318999
Inventors:
Anupama Suryanarayanan - Hillsboro OR, US
Matthew C. Merten - Hillsboro OR, US
Ryan L. Carlson - Hillsboro OR, US
International Classification:
G06F 1/28
G06F 1/26
G06F 12/08
G06F 1/32
Abstract:
In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.

Method, Apparatus, And System For Energy Efficiency And Energy Conservation Including Detecting And Controlling Current Ramps In Processing Circuit

View page
US Patent:
20150346804, Dec 3, 2015
Filed:
Aug 11, 2015
Appl. No.:
14/823994
Inventors:
Anupama Suryanarayanan - Hillsboro OR, US
Matthew C. Merten - Hillsboro OR, US
Ryan L. Carlson - Hillsboro OR, US
Stephen H. Gunther - Beaverton OR, US
International Classification:
G06F 1/32
Abstract:
Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value.

Computing System And Processor With Fast Power Surge Detection And Instruction Throttle Down To Provide For Low Cost Power Supply Unit

View page
US Patent:
20140095905, Apr 3, 2014
Filed:
Sep 28, 2012
Appl. No.:
13/631824
Inventors:
Krishnakanth Sistla - Beaverton OR, US
Martin Mark Rowland - Beaverton OR, US
Efraim Rotem - Haifa, IL
Brian J. Griffith - Auburn WA, US
Ankush Varma - Hillsboro OR, US
Anupama Suryanarayanan - Hillsboro OR, US
International Classification:
G06F 1/26
US Classification:
713320
Abstract:
A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.
Control profile
Anupama Suryanarayanan from Paramus, NJ, age ~38 Get Report