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Arvind K Sujeeth

from San Francisco, CA
Age ~39
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Also known as:
Arvind Krishna Sujeeth, Puthalath Sujeeth
Related to:
Frances Kramer Sulyok, 87Ethel KramerSusan Mickley, 42Amy M Cross, 42Melissa Conner, 44Roseann Nilges, 71Ronald L Nilges, 69
Connected to:
Veronica E Sujewicz, 34Ann J Suji, 43Keiko Sujino, 57George Sujitha, 59Narayan B Sujith, 34Thankappan Sujith, 86Anthony J Sujka, 98Kim Sujka, 40Robert J Sujka, 71Abul B Sujon, 36

Arvind Sujeeth Phones & Addresses

  • San Francisco, CA
  • Ballwin, MO
  • Maryland Heights, MO
  • Round Rock, TX
  • Austin, TX
  • Maryland Hts, MO

Work

Company: Sambanova systems May 2019 Position: Senior director of software

Education

Degree: Master of Science, Doctorates, Masters, Doctor of Philosophy School / High School: Stanford University 2008 to 2014 Specialities: Electrical Engineering, Philosophy, Computer Systems

Skills

Programming Languages • Domain Specific Languages • Parallel Programming • Distributed Systems • Machine Learning • Compilers • High Performance Computing • Data Mining • Algorithms • Hadoop • Programming • Linux • Computer Science • Python • Software Engineering • Functional Programming • Scala • Java • Amazon Web Services • Docker • Microservices

Industries

Computer Software

Resumes

Resumes

Arvind Sujeeth Photo 1

Senior Director Of Software

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Location:
San Francisco, CA
Industry:
Computer Software
Work:
Sambanova Systems
Senior Director of Software
Sambanova Systems Apr 2018 - May 2019
Director of Software
Mines.io Apr 1, 2014 - Jul 2018
Cofounder and Chief Technology Officer
Stanford University Sep 2008 - Jun 2014
Research Assistant
Education:
Stanford University 2008 - 2014
Master of Science, Doctorates, Masters, Doctor of Philosophy, Electrical Engineering, Philosophy, Computer Systems The University of Texas at Austin 2003 - 2007
Bachelors, Bachelor of Science, Computer Engineering
Skills:
Programming Languages
Domain Specific Languages
Parallel Programming
Distributed Systems
Machine Learning
Compilers
High Performance Computing
Data Mining
Algorithms
Hadoop
Programming
Linux
Computer Science
Python
Software Engineering
Functional Programming
Scala
Java
Amazon Web Services
Docker
Microservices

Publications

Us Patents

Lossless Tiling In Convolution Networks - Tiling Configuration For A Sequence Of Sections Of A Graph

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US Patent:
20220309316, Sep 29, 2022
Filed:
Jun 30, 2021
Appl. No.:
17/364110
Inventors:
- Palo Alto CA, US
Ruddhi CHAPHEKAR - Santa Clara CA, US
Ram SIVARAMAKRISHNAN - San Jose CA, US
Raghu PRABHAKAR - San Jose CA, US
Sumti JAIRATH - Santa Clara CA, US
Adi FUCHS - West Windsor NJ, US
Matheen MUSADDIQ - Austin TX, US
Arvind Krishna SUJEETH - San Francisco CA, US
Assignee:
SambaNova Systems, Inc. - Palo Alto CA
International Classification:
G06N 3/04
Abstract:
Disclosed is a data processing system that includes compile time logic to section a graph into a sequence of sections including a first section and a second section. The compile time logic is to configure the first section with a first topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the first section, and configure the second section with a second topology of tiling configurations in which to tile inputs, intermediate outputs, and final outputs of the second section. The data processing system further includes runtime logic configured with the compile time logic to execute the first section to generate the inputs, intermediate outputs, and final outputs of the first section in the first topology of tiling configurations, and execute the second section to generate the inputs, intermediate outputs, and final outputs of the second section in the second topology of tiling configurations.

Lossless Tiling In Convolution Networks - Tiling Configuration Between Two Sections

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US Patent:
20220309317, Sep 29, 2022
Filed:
Jun 30, 2021
Appl. No.:
17/364129
Inventors:
- Palo Alto CA, US
Ruddhi CHAPHEKAR - Santa Clara CA, US
Ram SIVARAMAKRISHNAN - San Jose CA, US
Raghu PRABHAKAR - San Jose CA, US
Sumti JAIRATH - Santa Clara CA, US
Adi FUCHS - West Windsor NJ, US
Matheen MUSADDIQ - Austin TX, US
Arvind Krishna SUJEETH - San Francisco CA, US
Assignee:
SambaNova Systems, Inc. - Palo Alto CA
International Classification:
G06N 3/04
Abstract:
Disclosed is a method that includes sectioning a graph into a sequence of sections, the sequence of sections including at least a first section followed by a second section. The first section is configured to generate a first output in a first target tiling configuration in response to processing a first input in a first input tiling configuration. The graph is configured to reconfigure the first output in the first target tiling configuration to a second input in a second input tiling configuration. The second section is configured to generate a second output in a second target tiling configuration in response to processing the second input in the second input tiling configuration.

Lossless Tiling In Convolution Networks - Padding And Re-Tilling At Section Boundaries

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US Patent:
20220309318, Sep 29, 2022
Filed:
Jun 30, 2021
Appl. No.:
17/364141
Inventors:
- Palo Alto CA, US
Ruddhi CHAPHEKAR - Santa Clara CA, US
Ram SIVARAMAKRISHNAN - San Jose CA, US
Raghu PRABHAKAR - San Jose CA, US
Sumti JAIRATH - Santa Clara CA, US
Adi FUCHS - West Windsor NJ, US
Matheen MUSADDIQ - Austin TX, US
Arvind Krishna SUJEETH - San Francisco CA, US
Assignee:
SambaNova Systems, Inc. - Palo Alto CA
International Classification:
G06N 3/04
Abstract:
Disclosed is a method that includes generating by an output processing node of a first section of a processing graph, a plurality of output tiles of an output tensor. The plurality of output tiles of the output tensor is written in a memory, where the writing includes zero-padding the plurality of output tiles of the output tensor in the memory. The zero-padded plurality of output tiles of the output tensor are tiled, to generate a plurality of input tiles of an input tensor. The plurality of input tiles of the input tensor is processed in a second section of the processing graph.

Lossless Tiling In Convolution Networks - Section Boundaries

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US Patent:
20220309319, Sep 29, 2022
Filed:
Sep 16, 2021
Appl. No.:
17/477409
Inventors:
- Palo Alto CA, US
Ruddhi CHAPHEKAR - Santa Clara CA, US
Ram SIVARAMAKRISHNAN - San Jose CA, US
Raghu PRABHAKAR - San Jose CA, US
Sumti JAIRATH - Santa Clara CA, US
Adi FUCHS - West Windsor NJ, US
Matheen MUSADDIQ - Austin TX, US
Arvind Krishna SUJEETH - San Francisco CA, US
Assignee:
SambaNova Systems, Inc. - Palo Alto CA
International Classification:
G06N 3/04
Abstract:
Disclosed is a data processing system that includes compile time logic to section a graph into a sequence of sections, configure a first section to generate a first set of output tiles in a first target tiling configuration in response to processing a first set of input tiles in a first input tiling configuration, and configure a second section to generate a second set of output tiles in a second target tiling configuration in response to processing the first set of output tiles in a second input tiling configuration. Runtime logic is configured to pad a first input into a first padded input, read the first set of input tiles from the first padded input in the first input tiling configuration, and process the first set of input tiles through the first section to generate the first set of output tiles in the first target tiling configuration.

Lossless Tiling In Convolution Networks - Section Cuts

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US Patent:
20220309322, Sep 29, 2022
Filed:
Mar 4, 2022
Appl. No.:
17/687516
Inventors:
- Palo Alto CA, US
Ruddhi CHAPHEKAR - Santa Clara CA, US
Ram SIVARAMAKRISHNAN - San Jose CA, US
Raghu PRABHAKAR - San Jose CA, US
Sumti JAIRATH - Santa Clara CA, US
Adi FUCHS - West Windsor NJ, US
Matheen MUSADDIQ - Austin TX, US
Arvind Krishna SUJEETH - San Francisco CA, US
Assignee:
SambaNova Systems, Inc. - Palo Alto CA
International Classification:
G06N 3/04
Abstract:
A data processing system receives a graph that includes a sequence of layers and executes graph cuts between a preceding layer in the graph and a succeeding layer in the graph that succeeds the preceding layer. The preceding layer generates a set of tiles on a tile-by-tile basis and the succeeding layer processes a tensor that includes multiple tiles in the set of tiles. Thus the graph is partitioned into a sequence of subgraphs, and a subgraph in the sequence of subgraphs including a sub-sequence of layers in the sequence of layers. One or more configuration files is generated to configure runtime logic to execute the sequence of subgraphs and the one or more configuration files are stored on a computer-readable media.

Lossless Tiling In Convolution Networks - Data Flow Logic

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US Patent:
20220309323, Sep 29, 2022
Filed:
Mar 21, 2022
Appl. No.:
17/700336
Inventors:
- Palo Alto CA, US
Ruddhi CHAPHEKAR - Santa Clara CA, US
Ram SIVARAMAKRISHNAN - San Jose CA, US
Raghu PRABHAKAR - San Jose CA, US
Sumti JAIRATH - Santa Clara CA, US
Adi FUCHS - West Windsor NJ, US
Matheen MUSADDIQ - Austin TX, US
Arvind Krishna SUJEETH - San Francisco CA, US
Assignee:
SambaNova Systems, Inc. - Palo Alto CA
International Classification:
G06N 3/04
Abstract:
A data processing system includes memory and reconfigurable processors, operatively coupled to the memory, configured to execute a sequence of subgraphs of a graph. The sequence of subgraphs includes a preceding subgraph and a succeeding subgraph. The data processing system also includes data flow logic, operatively coupled to the reconfigurable processors and the memory, configured to store a tiled output of the preceding subgraph as a composed input in the memory and make available parts of the composed input for processing by the succeeding subgraph.

Lossless Tiling In Convolution Networks - Graph Metadata Generation

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US Patent:
20220309324, Sep 29, 2022
Filed:
Mar 21, 2022
Appl. No.:
17/700452
Inventors:
- Palo Alto CA, US
Ruddhi CHAPHEKAR - Santa Clara CA, US
Ram SIVARAMAKRISHNAN - San Jose CA, US
Raghu PRABHAKAR - San Jose CA, US
Sumti JAIRATH - Santa Clara CA, US
Adi FUCHS - West Windsor NJ, US
Matheen MUSADDIQ - Austin TX, US
Arvind Krishna SUJEETH - San Francisco CA, US
Assignee:
SambaNova Systems, Inc. - Palo Alto CA
International Classification:
G06N 3/04
Abstract:
A processing graph of an application with a sequence of processing nodes is obtained which processes an input and generates an intermediate representation a further intermediate representation, and an output representation of the input at stages in the sequence of processing nodes. Graph metadata is generated that specifies a non-overlapping target tiling configuration for the output representation, an overlapping tiling configuration for the input, an overlapping tiling configuration for the intermediate representation, and a third tiling configuration for the further intermediate representation. The processing graph is modified based on the graph metadata to conform to the parameters specified by the graph metadata. A set of computer instructions is then created to execute the modified processing graph on a target processing system.

Lossless Tiling In Convolution Networks - Resetting Overlap Factor To Zero At Section Boundaries

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US Patent:
20220309325, Sep 29, 2022
Filed:
Apr 4, 2022
Appl. No.:
17/713157
Inventors:
- Palo Alto CA, US
Ruddhi CHAPHEKAR - Santa Clara CA, US
Ram SIVARAMAKRISHNAN - San Jose CA, US
Raghu PRABHAKAR - San Jose CA, US
Sumti JAIRATH - Santa Clara CA, US
Adi FUCHS - West Windsor NJ, US
Matheen MUSADDIQ - Austin TX, US
Arvind Krishna SUJEETH - San Francisco CA, US
Assignee:
SambaNova Systems, Inc. - Palo Alto CA
International Classification:
G06N 3/04
Abstract:
A data processing system includes compile time logic to section a graph into a sequence of sections, including a first section followed by a second section. The compile time logic configured the first section to generate a first output in a first non-overlapping target configuration in response to processing an input in a first overlapping input configuration, and configures the second section to generate a second output in a second non-overlapping target configuration in response to processing the first output in a second overlapping input configuration. The compile time logic also creates a set of computer instructions to execute the first section and the second section on a target processing system.
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Arvind K Sujeeth from San Francisco, CA, age ~39 Get Report