Babak Matinpour

7994807, Aug 9, 2011

Oct 23, 2007

11/877519

Yongseon Koh - Palo Alto CA, US
Babak Matinpour - Sunnyvale CA, US
Vijaya Ceekala - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

G01R 31/3187

3247503, 32476301, 32476201, 324500, 327108, 327333

An analog device under test circuit and a built-in test circuit for testing an AC transfer characteristic of the analog device under test are fabricated on an integrated circuit. The built-in test circuit includes an amplitude detector that detects the amplitude of the output signal of the analog device under test. The test time is reduced by sampling in real-time the DC value corresponding to the amplitude of the analog device under test. An additional reduction in the test time is achieved by using comparators with upper and lower limit reference signals and a pass-fail logic test.

20040014446, Jan 22, 2004

May 8, 2003

10/431925

Sudipto Chakraborty - Atlanta GA, US
Babak Matinpour - Atlanta GA, US
Joy Laskar - Atlanta GA, US

H04B017/00

455/226400, 455/249100

A higher frequency modulator built with low cost materials and with a lower power requirement is described as well as methods relating thereto. A received radio frequency (RF) signal is combined with a created local oscillator (LO) signal to result in a combined radio frequency (RF) signal, which may be converted into a message signal. A subharmonic mixer may be used to convert the combined RF signal into the message signal. The subharmonic mixer may include antiparallel diode pair (APDP) topology. The created LO signal is a combination of a selected LO signal with another LO signal. The selected LO signal may be a subharmonic of the RF signal. The other LO signal may be a low odd-order harmonic of the selected LO signal. Preferably, the created LO signal is not greater than the RF signal.

7649409, Jan 19, 2010

Oct 23, 2007

11/877255

Yongseon Koh - Palo Alto CA, US
Babak Matinpour - Sunnyvale CA, US
Vijaya Ceekala - San Jose CA, US
Ramsin Ziazadeh - San Jose CA, US

National Semiconductor Corporation - Santa Clara CA

H03B 1/00

327559, 326 30

An integrated circuit comprises a pin coupled to receive signals from outside the integrated circuit and an input network. The input network equalizes incoming signals by attenuating lower frequency input signals more than higher frequency input signals received at the pin. The input network is configured to generate a DC bias voltage at an output of the input network in response to an AC coupled input signal or a DC coupled input signal received at the pin with a wide common-mode range.