Benjamin S Mckee

7892908, Feb 22, 2011

Dec 24, 2008

12/343794

Angelo Pinto - San Diego CA, US
Frank S. Johnson - Wappingers Falls NY, US
Benjamin P. McKee - Richardson TX, US
Shaofeng Yu - Plano TX, US

Texas Instruments Incorporated - Dallas TX

H01L 21/8238
H01L 21/335

438199, 438221, 438233, 438275, 438296, 438424, 257E21633, 257E21618

Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming ()-oriented silicon regions for NMOS and () regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has () and ()-oriented regions. The method forms a directly bonded silicon (DSB) layer of ()-oriented silicon on a ()-oriented substrate. The DSB layer is removed in the NMOS regions and a ()-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

8558318, Oct 15, 2013

Jan 14, 2011

13/007098

Angelo Pinto - San Diego CA, US
Frank S Johnson - Wappingers Falls NY, US
Benjamin P McKee - Richardson TX, US
Shaofeng Yu - Plano TX, US

Texas Instruments Incorporated - Dallas TX

H01L 27/01
H01L 27/12
H01L 29/76
H01L 29/94
H01L 31/062

257369, 257274, 257371, 257351

Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.