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Beomseok Choi

from Phoenix, AZ
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Connected to:
Aelim Choi, 37Aesun Choi, 65Ashely D Choi, 50Becky L Choi, 66Benedicta K Choi, 39Byongho H Choi, 53Byoungman M Choi, 57Byungdae Choi, 37Cecil W Choi, 46Celia Choi, 27

Beomseok Choi Phones & Addresses

  • Phoenix, AZ
  • Boulder, CO

Work

Company: Intel corporation Sep 2015 Position: Analog engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of Colorado Boulder 2015 to 2015 Specialities: Energy, Engineering, Philosophy

Skills

Analog Circuit Design • Power Electronics • Matlab • Simulations • Simulink • Labview • Mixed Signal Ic Design • Electrical Engineering • Verilog • Analog • Circuit Design • Electronics • Semiconductors • C • C++ • Digital Designs • Video Coding • Integrated Circuit Design • Power Delivery • Signal Processing • Fpga • Dsp • Microcontrollers • Programming • Pcb Design • Ic • Packaging Design • Latex • Pspice • Spice • Cadence • Cmos • Semiconductor Packaging • Power Integrity • Mentor Graphics • Powersi • Hfss

Languages

Korean • English

Industries

Semiconductors

Resumes

Resumes

Beomseok Choi Photo 1

Analog Engineer

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Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Intel Corporation
Analog Engineer
University of Colorado Boulder Aug 2011 - Aug 2015
Research Assistant
Texas Instruments May 2014 - Aug 2014
Internship
Qualcomm May 2012 - Aug 2012
Internship
Keti(Korea Electronics Technology Institute) 2008 - 2010
Assistant Researcher
Education:
University of Colorado Boulder 2015 - 2015
Doctorates, Doctor of Philosophy, Energy, Engineering, Philosophy Kyung Hee University 2009 - 2009
Master of Science, Masters, Engineering, Electronics Kyung Hee University 2006 - 2006
Bachelors, Bachelor of Science, Engineering, Electronics
Skills:
Analog Circuit Design
Power Electronics
Matlab
Simulations
Simulink
Labview
Mixed Signal Ic Design
Electrical Engineering
Verilog
Analog
Circuit Design
Electronics
Semiconductors
C
C++
Digital Designs
Video Coding
Integrated Circuit Design
Power Delivery
Signal Processing
Fpga
Dsp
Microcontrollers
Programming
Pcb Design
Ic
Packaging Design
Latex
Pspice
Spice
Cadence
Cmos
Semiconductor Packaging
Power Integrity
Mentor Graphics
Powersi
Hfss
Languages:
Korean
English

Publications

Us Patents

Waveguide Interconnects For Semiconductor Packages And Related Methods

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US Patent:
20220416393, Dec 29, 2022
Filed:
Jun 25, 2021
Appl. No.:
17/359138
Inventors:
- Santa Clara CA, US
Johanna Swan - Scottsdale AZ, US
Adel Elsherbini - Tempe AZ, US
Shawna Liff - Scottsdale AZ, US
Beomseok Choi - Chandler AZ, US
Qiang Yu - Saratoga CA, US
International Classification:
H01P 3/16
H01L 25/065
H01P 1/208
H01L 23/538
H01P 5/107
H01L 23/66
Abstract:
Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

Conformal Power Delivery Structures Including Embedded Passive Devices

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US Patent:
20230095608, Mar 30, 2023
Filed:
Sep 24, 2021
Appl. No.:
17/485250
Inventors:
- Santa Clara CA, US
Aleksandar Aleksov - Chandler AZ, US
Feras Eid - Chandler AZ, US
Henning Braunisch - Phoenix AZ, US
Thomas L. Sounart - Chandler AZ, US
Johanna Swan - Scottsdale AZ, US
Beomseok Choi - Chandler AZ, US
Krishna Bharath - Phoenix AZ, US
William J. Lambert - Tempe AZ, US
Kaladhar Radhakrishnan - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H05K 3/14
H05K 3/10
H05K 3/30
H01L 21/768
H01L 21/82
Abstract:
A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.

Conformal Power Delivery Structures

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US Patent:
20230095654, Mar 30, 2023
Filed:
Sep 24, 2021
Appl. No.:
17/484213
Inventors:
- Santa Clara CA, US
Feras Eid - Chandler AZ, US
Stephen Morein - San Jose CA, US
Krishna Bharath - Phoenix AZ, US
Henning Braunisch - Phoenix AZ, US
Beomseok Choi - Chandler AZ, US
Brandon M. Rawlings - Chandler AZ, US
Thomas L. Sounart - Chandler AZ, US
Johanna Swan - Scottsdale AZ, US
Yoshihiro Tomita - Tsukuba-Shi, JP
Aleksandar Aleksov - Chandler AZ, US
International Classification:
H01L 23/498
H01L 23/48
H01L 25/065
H01L 21/48
Abstract:
In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

In Situ Inductor Structure In Buildup Power Planes

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US Patent:
20230096368, Mar 30, 2023
Filed:
Sep 24, 2021
Appl. No.:
17/485243
Inventors:
- Santa Clara CA, US
Adel Elsherbini - Chandler AZ, US
Johanna Swan - Scottsdale AZ, US
Feras Eid - Chandler AZ, US
Thomas L. Sounart - Chandler AZ, US
Henning Braunisch - Phoenix AZ, US
Beomseok Choi - Chandler AZ, US
Krishna Bharath - Phoenix AZ, US
Kaladhar Radhakrishnan - Chandler AZ, US
William J. Lambert - Tempe AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 49/02
H01F 27/255
H01F 27/28
H01F 41/04
H01F 41/02
H01L 23/498
H01L 23/64
H01L 21/48
Abstract:
An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.

Conformal Power Delivery Structure For Direct Chip Attach Architectures

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US Patent:
20230097714, Mar 30, 2023
Filed:
Sep 24, 2021
Appl. No.:
17/485208
Inventors:
- Santa Clara CA, US
Beomseok Choi - Chandler AZ, US
Krishna Bharath - Phoenix AZ, US
Kaladhar Radhakrishnan - Chandler AZ, US
Adel Elsherbini - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/538
H01L 25/065
H01L 23/00
Abstract:
In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

High-Throughput Additively Manufactured Power Delivery Vias And Traces

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US Patent:
20210407903, Dec 30, 2021
Filed:
Jun 26, 2020
Appl. No.:
16/914062
Inventors:
- Santa Clara CA, US
Feras Eid - Chandler AZ, US
Henning Braunisch - Phoenix AZ, US
Beomseok Choi - Chandler AZ, US
William J. Lambert - Tempe AZ, US
Stephen Morein - Chandler AZ, US
Ahmed Abou-Alfotouh - Chandler AZ, US
Johanna Swan - Scottsdale AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/522
H01L 23/532
H05K 1/11
H05K 3/14
H01L 21/768
Abstract:
An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

Power Delivery Structures

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US Patent:
20210398895, Dec 23, 2021
Filed:
Jun 22, 2020
Appl. No.:
16/907797
Inventors:
- Santa Clara CA, US
Feras Eid - Chandler AZ, US
Beomseok Choi - Chandler AZ, US
Henning Braunisch - Phoenix AZ, US
William Lambert - Tempe AZ, US
Krishna Bharath - Chandler AZ, US
Johanna Swan - Scottsdale AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/50
H05K 1/18
H01L 23/367
H01L 23/31
H01L 23/48
H01L 23/00
H01L 25/065
H01L 21/48
H01L 21/56
H01L 25/00
Abstract:
An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

Reconfigurable Inductor

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US Patent:
20210036618, Feb 4, 2021
Filed:
Sep 28, 2017
Appl. No.:
16/642268
Inventors:
- Santa Clara CA, US
Kaladhar Radhakrishnan - Chandler AZ, US
Beomseok Choi - Chandler AZ, US
Krishna Bharath - Chandler AZ, US
Michael J. Hill - Gilbert AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H02M 3/158
G01R 19/165
G05F 1/46
H01F 21/02
Abstract:
An adjustable inductance system includes a plurality of inductor modules coupled to a corresponding plurality of loads and a pool of at least one floating inductor module that may be coupled in parallel with any one of the plurality of inductor modules. A control circuit monitors the current drawn through the inductor module by the load. If current draw exceeds a threshold, the control circuit couples a floating inductor module to the load. Using the current drawn by the load, the control circuit determines an appropriate inductance value and determines an appropriate inductor configuration for the inductor module, the floating inductor module, or both the inductor module and the floating inductor module to achieve the determined inductance value. The control circuit causes switching elements to transition to a state or position to achieve the inductor configuration.
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Beomseok Choi from Phoenix, AZ Get Report