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Bertrand F Cambou

from Providence, RI
Age ~68
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Also known as:
Bertrand Francis Cambou, Bertrand Elaine Cambou, Bertrand Line Cambou, Bertrand S Cambou, Bertrand C Cambou, Betrand F Cambou, Bertand Cambou, Cambou Bertrand
Related to:
Xavier Cambou, 41Felix Bertrand Cambou, 37Line CambouElaine BibowAnne Cambou, 43
Connected to:
Stephane C Cambourakis, 67Kirandeep K Cambow, 31Benford Cambra, 34Brandi L Cambra, 52Helene M Cambra, 62Kathie J Cambra, 69Lorraine A Cambra, 91Lucianna M Cambra, 58Margaret A Cambra, 67

Bertrand Cambou Phones & Addresses

  • Providence, RI
  • Flagstaff, AZ
  • Northampton, MA
  • 2510 Waverley St, Palo Alto, CA 94301
  • Santa Clara, CA
  • Austin, TX
  • Coronado, AZ
  • 101 Alma St APT 1201, Palo Alto, CA 94301

Work

Company: Crocus technology Jan 1, 2010 to Apr 2015 Position: Executive chairman

Education

Degree: Doctorates School / High School: Paris - Sud University (Paris Xi) 1977 to 1981 Specialities: Physics

Skills

Asic • Analog • Strategic Partnerships • Management • Semiconductors • Semiconductor Industry • Business Strategy • Strategy • Product Management • Cross Functional Team Leadership • Product Development • Mixed Signal • Ic • Product Marketing • Program Management • Wireless • Flash Memory • Eda • Soc • Start Ups • Leadership • Cybersecurity • Cryptography • Hardware Security • Nanotechnologies • Nanoelectronics

Industries

Semiconductors

Resumes

Resumes

Bertrand Cambou Photo 1

Bertrand Cambou

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Location:
101 Alma St, Palo Alto, CA 94301
Industry:
Semiconductors
Work:
Crocus Technology Jan 1, 2010 - Apr 2015
Executive Chairman
Stt 2009 - 2010
President
Amd 2002 - 2008
President Spansion
Gemplus 1999 - 2001
Chief Operations Officer
Motorola 1984 - 1999
Senior Vice President Ncsg
Education:
Paris - Sud University (Paris Xi) 1977 - 1981
Doctorates, Physics Centralesupelec 1977 - 1979
Paris Xi University
Doctorates, Doctor of Philosophy, Electrical Engineering, Physics Toulouse University
Master of Science, Masters, Physics
Skills:
Asic
Analog
Strategic Partnerships
Management
Semiconductors
Semiconductor Industry
Business Strategy
Strategy
Product Management
Cross Functional Team Leadership
Product Development
Mixed Signal
Ic
Product Marketing
Program Management
Wireless
Flash Memory
Eda
Soc
Start Ups
Leadership
Cybersecurity
Cryptography
Hardware Security
Nanotechnologies
Nanoelectronics

Business Records

Name / Title
Company / Classification
Phones & Addresses
Bertrand F. Cambou
President
Microchip Technology Incorporated
Mfg Semiconductors/Related Devices
450 Holger Way, San Jose, CA 95134
(408) 735-9110
Bertrand F. Cambou
President
Bfc-Alto Solutions, Inc
Nonclassifiable Establishments
2510 Waverley St, Palo Alto, CA 94301

Publications

Us Patents

Memory Array Including Magnetic Random Access Memory Cells And Oblique Field Lines

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US Patent:
8587079, Nov 19, 2013
Filed:
Aug 10, 2012
Appl. No.:
13/572566
Inventors:
Bertrand F. Cambou - Palo Alto CA, US
Douglas J. Lee - San Jose CA, US
Anthony J. Tether - Falls Church VA, US
Barry Hoberman - Cupertino CA, US
Assignee:
Crocus Technology Inc. - Santa Clara CA
International Classification:
H01L 27/22
US Classification:
257422, 257E27005
Abstract:
A memory device includes a first plurality of magnetic random access memory (MRAM) cells positioned along a first direction, and a first bit line electrically connected to the first plurality of MRAM cells, the bit line oriented in the first direction. The device includes a first plurality of field lines oriented in a second direction different from the first direction, the first plurality of field lines being spaced such that only a corresponding first one of the first plurality of MRAM cells is configurable by each of the first plurality of field lines. The device includes a second plurality of field lines oriented in a third direction different from the first direction and the second direction, the second plurality of field lines being spaced such that only a corresponding second one of the first plurality of MRAM cells is configurable by each of the second plurality of field lines.

Multilevel Magnetic Element

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US Patent:
8630112, Jan 14, 2014
Filed:
Oct 26, 2011
Appl. No.:
13/281507
Inventors:
Bertrand Cambou - Palo Alto CA, US
Assignee:
Crocus Technology SA - Grenoble Cedex
International Classification:
G11C 11/00
US Classification:
365158, 365148, 365171, 365172, 977933, 977935
Abstract:
The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.

Stress Management In Bga Packaging

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US Patent:
20080142956, Jun 19, 2008
Filed:
Dec 19, 2006
Appl. No.:
11/641506
Inventors:
Bertrand F. Cambou - Palo Alto CA, US
Lam Tim Fai - Suzhou, CN
International Classification:
H01L 23/34
US Classification:
257723
Abstract:
The present semiconductor structure includes a substrate having a planar surface, a semiconductor chip attached to the planar surface of the substrate, the chip preferably being of the same thickness as or thinner than the substrate, and a package body attached to the substrate and to the semiconductor chip. The semiconductor chip and substrate are sufficiently rigidly attached so that substantial force applied parallel to the planar surface of the substrate may be transmitted therebetween, reducing temperature-change stress on solder balls which connect the substrate with a PCB. The semiconductor chip with advantage is thinned to reduce the stress on the solder balls.

Apparatus, System, And Method For Matching Patterns With An Ultra Fast Check Engine Based On Flash Cells

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US Patent:
20120143554, Jun 7, 2012
Filed:
Dec 1, 2011
Appl. No.:
13/309475
Inventors:
Bertrand F. Cambou - Palo Alto CA, US
Neal Berger - Cupertino CA, US
Mourad El Baraji - Sunnyvale CA, US
Assignee:
CROCUS TECHNOLOGY, INC. - Sunnyvale CA
International Classification:
G06F 19/00
US Classification:
702113
Abstract:
A check engine includes a plurality of comparators, each including a plurality of flash cells, where each of the plurality of comparators is configured to store at least one reference bit included in a set of reference bits, and includes an input for presenting at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

Apparatus, System, And Method For Matching Patterns With An Ultra Fast Check Engine

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US Patent:
20120143889, Jun 7, 2012
Filed:
Dec 1, 2011
Appl. No.:
13/309369
Inventors:
Bertrand F. Cambou - Palo Alto CA, US
Neal Berger - Cupertino CA, US
Mourad El Baraji - Fremont CA, US
Assignee:
CROCUS TECHNOLOGY, INC. - Sunnyvale CA
International Classification:
G06F 17/30
US Classification:
707758, 707E17009
Abstract:
A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

Magnetic Random Access Memory Cell With A Dual Junction For Ternary Content Addressable Memory Applications

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US Patent:
20120250391, Oct 4, 2012
Filed:
Mar 27, 2012
Appl. No.:
13/430963
Inventors:
Bertrand Cambou - Palo Alto CA, US
Assignee:
CROCUS TECHNOLOGY SA - Grenoble
International Classification:
G11C 11/22
US Classification:
365145
Abstract:
The present disclosure concerns a MRAM cell comprising a first tunnel barrier layer comprised between a soft ferromagnetic layer having a free magnetization and a first hard ferromagnetic layer having a first storage magnetization; a second tunnel barrier layer comprised between the soft ferromagnetic layer and a second hard ferromagnetic layer having a second storage magnetization; the first storage magnetization being freely orientable at a first high predetermined temperature threshold and the second storage magnetization being freely orientable at a second predetermined high temperature threshold; the first high predetermined temperature threshold being higher than the second predetermined high temperature threshold. The MRAM cell can be used as a ternary content addressable memory (TCAM) and store up to three distinct state levels. The MRAM cell has a reduced size and can be made at low cost.

Salted Hashing Method For Response-Based Cryptography

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US Patent:
20230038135, Feb 9, 2023
Filed:
Jul 22, 2022
Appl. No.:
17/871850
Inventors:
- Flagstaff AZ, US
Bertrand F. Cambou - Flagstaff AZ, US
Kaitlyn Lee - Flagstaff AZ, US
Christopher R. Philabaum - Flagstaff AZ, US
International Classification:
H04L 9/32
H04L 9/08
H04L 9/06
Abstract:
Systems and methods for cryptographic key generation at a client and server are disclosed. The client has an array of PUF devices, and the server has an image that PUF. The server sends the client addresses of PUF devices to be measured, and retrieves previously stored responses corresponding to those addresses from its database. The client measures responses at the addresses. Each device hashes the resulting responses, and the server compares the hash received from the client to its own. If the hashes to not match, the server searches for a matching hash be perturbing the measured response bit stream until a match is achieved. The perturbed response bitstream, and the measured response at the client are then salted, and used for key generation.

Fast Cryptographic Key Generation From Memristor-Based Physical Unclonable Computed Functions

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US Patent:
20210314176, Oct 7, 2021
Filed:
Apr 2, 2021
Appl. No.:
17/221180
Inventors:
- Flagstaff AZ, US
Bertrand F. Cambou - Flagstaff AZ, US
International Classification:
H04L 9/32
G06F 11/10
Abstract:
Systems and methods for symmetric encryption between a client and a server device include a client device having an array of physical unclonable function devices and a server device storing information sufficient to reconstruct responses of the devices to an applied stimulus such as varying levels of electrical current. The server shares a challenge with the client, which measures characteristics such as electrical resistances for a subset of the devices according to instructions extracted from the challenge. The client measures a corresponding reference device in the array for each device of the subset and assigns a value determined based on a comparison of each device with the corresponding reference device to generate a cryptographic key. The server calculates an expected response of the client to the challenge according to a model of the devices in the array, and uses the calculated response to generate the key independently.
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Bertrand F Cambou from Providence, RI, age ~68 Get Report