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Bidyut K Sen

from Milpitas, CA
Age ~67
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Also known as:
Bidyut F Sen, Bidyut Dutta
Phone and address:
1151 Park Grove Dr, Milpitas, CA 95035
(408) 263-7851
Related to:
April Dutta, 69
Connected to:
Ahana Sen, 30Amartya Sen, 33Anurupa Sen, 44Avishek Sen, 38Aysegul S Sen, 34Bikram R Sen, 50Dana Sen, 34Debasree Sen, 37Gargi Sen, 62Ha Y Sen, 70

Bidyut Sen Phones & Addresses

  • 1151 Park Grove Dr, Milpitas, CA 95035 (408) 263-7851
  • Fremont, CA
  • 1151 Park Grove Dr, Milpitas, CA 95035 (408) 499-1069

Education

Degree: High school graduate or higher

Emails

a***[email protected]

Resumes

Resumes

Bidyut Sen Photo 1

Director, Semiconductor Packaging And Pcb Technology

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Location:
Milpitas, CA
Industry:
Computer Hardware
Work:
Sun Microsystems 1997 - 2002
Senior Staff Engineer
Oracle 1997 - 2002
Director, Semiconductor Packaging and Pcb Technology
Fujitsu Computer Packaging Technology 1995 - 1997
Director of Marketing
Fujitsu Computer Packaging Technology 1992 - 1995
Senior Scientist
Lsi Corporation 1988 - 1992
Manager, Simulation and Characterization
Education:
Stony Brook University 1979 - 1986
Doctorates, Doctor of Philosophy, Physics, Philosophy Indian Institute of Technology, Kanpur 1977 - 1979
Master of Science, Masters, Physics
Skills:
Asic
Pcb Design
Semiconductors
Signal Integrity
Microprocessors
Hardware
Reliability
Packaging
Thermal Analysis
Flip Chip
Assembly
High Speed Design
Mechanical
Supplier Management
Mcms
Tsv
Electrical
Bidyut Sen Photo 2

Bidyut Sen

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Bidyut Sen Photo 3

Bidyut Sen

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Publications

Us Patents

Efficient Device Debug System

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US Patent:
6472900, Oct 29, 2002
Filed:
Jun 4, 2001
Appl. No.:
09/874188
Inventors:
Deviprasad Malladi - Campbell CA
Shahid Ansari - Milpitas CA
Hanxi Chen - San Jose CA
Bidyut Sen - Milpitas CA
Steven Boyle - Santa Clara CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G01R 3126
US Classification:
324765, 257700
Abstract:
A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Method Of Emulating An Ideal Transformer Valid From Dc To Infinite Frequency

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US Patent:
6754616, Jun 22, 2004
Filed:
Jan 31, 2000
Appl. No.:
09/494821
Inventors:
Bidyut K. Sen - Milpitas CA
James C. Parker - late of Pleasanton CA
Richard L. Wheeler - Pleasanton CA
Assignee:
Fujitsu Limited - Kawasaki
International Classification:
G06G 762
US Classification:
703 13, 703 14, 703 18, 703 23, 716 1, 716 11
Abstract:
A method of simulating the electrical behavior of an ideal transformer. The representation of the ideal transformer is frequency independent and can be used to simulate the behavior of an ideal transformer over the frequency range from DC to infinity. In one embodiment, the ideal transformer is represented as having an input sub-circuit and an output sub-circuit. Each sub-circuit includes a resistor connected in parallel across a current controlled current source. The input current, output current, current sources, and resistances are scaled by a scaling factor representing the turns ratio between the primary and secondary windings of a physical transformer. In the present invention, the current sources are responsible for the current scaling and the resistors are responsible for the impedance scaling. The circuit elements of the representation may be used as the basis for generating a set of input parameters for a circuit emulation program.

Multipoint Plane Measurement Probe And Methods Of Characterization And Manufacturing Using Same

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US Patent:
6894513, May 17, 2005
Filed:
Jan 27, 2003
Appl. No.:
10/351883
Inventors:
Bidyut Sen - Milpitas CA, US
Sreemala Pannala - Sunnyvale CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G01R031/26
G01R027/08
US Classification:
324719, 324715, 324754
Abstract:
The present application describes a method and an apparatus for characterizing a conductive plane using multipoint measurement. In an embodiment of the present invention, a known current is injected in the conductive plane using multipoint probes and voltage is measured using multipoint probes. The electrical characteristics of the plane can be determined using the values of the known current, measured voltage and the distance between the probes. In an embodiment of the present invention, the conductive plane is integrated in a semiconductor package of an integrated circuit and the value of the known current is determined based on the actual current that can be provided by the integrated circuit during normal operation.

Method To Test Power Distribution System

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US Patent:
6925616, Aug 2, 2005
Filed:
Oct 4, 2002
Appl. No.:
10/265035
Inventors:
Leesa Noujeim - Sunnyvale CA, US
Bidyut K. Sen - Milpitas CA, US
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G06F017/50
G01R013/02
G01R031/08
US Classification:
716 4, 716 5, 716 18, 324 7655, 324512, 324645, 438 14, 438484
Abstract:
A method for testing a core power distribution system for an integrated circuit chip which includes arranging a plurality of experiments for an integrated circuit chip, performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances, generating a schmoo diagram for each of the plurality of experiments, and analyzing the schmoo diagrams to determine whether the core power distribution system functions is acceptable at a particular frequency.

Emi Grounding Pins For Cpu/Asic Chips

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US Patent:
6956285, Oct 18, 2005
Filed:
Jan 15, 2003
Appl. No.:
10/345015
Inventors:
Sergiu Radu - Fremont CA, US
Bidyut K. Sen - Milpitas CA, US
David Hockanson - Boulder Creek CA, US
John E. Will - Pleasanton CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
H01L023/48
H01L023/12
H01L023/06
H01L023/52
US Classification:
257697, 257660, 257704, 257707, 257713, 257778, 257659
Abstract:
An integrated circuit package includes EMI containment features. The EMI containment features may include a plurality of pins on a substrate of the integrated circuit package. The pins may be a peripheral row of pins in an array of pins. The pins may couple a lid of the package to at least one ground plane of a circuit board.

Conformal Heat Spreader

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US Patent:
7007741, Mar 7, 2006
Filed:
Oct 18, 2002
Appl. No.:
10/273615
Inventors:
Bidyut K. Sen - Milpitas CA, US
Scott Kirkman - Menlo Park CA, US
Vadim Gektin - San Jose CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
F28F 7/00
US Classification:
165 46, 165185, 165 804
Abstract:
A heat spreader apparatus for cooling an electronic component and method of attachment. The heat spreader comprises a flexible wall that partially conforms to a non-matching mating surface of the component when pressure is applied to the surface of the flexible wall that is opposite the component. The pressure may be maintained against the flexible wall during use, or released once the flexible wall is maintained in its conforming location by an adhesive.

Mechanism For Determining An Accelerated Test Specification For Device Elements

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US Patent:
7571059, Aug 4, 2009
Filed:
Jun 28, 2006
Appl. No.:
11/477235
Inventors:
Ron Zhang - Sunnyvale CA, US
Bidyut Sen - Milpitas CA, US
Assignee:
Sun Microsystems, Inc. - Santa Clara CA
International Classification:
G01B 3/44
US Classification:
702 34
Abstract:
A mechanism is disclosed for determining an accelerated test for a device. The method comprises calculating an estimated amount of damage that an element of the device would suffer if the device were operated under a set of specified conditions over a certain period of time (e. g. , expected lifetime of the device). The method further comprises determining an accelerated test to which to subject the element in order to cause the element to suffer an actual amount of damage that is approximately equal to the estimated amount of damage. The accelerated test may be an accelerated test cycle, such as an accelerated temperature cycle.

Ternary Alloy Column Grid Array

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US Patent:
7754343, Jul 13, 2010
Filed:
Dec 21, 2005
Appl. No.:
11/315818
Inventors:
David Love - Pleasanton CA, US
Bidyut Sen - Milpitas CA, US
Assignee:
Oracle America, Inc. - Redwood City CA
International Classification:
B23K 35/22
H01L 23/48
B22F 7/02
B32B 3/00
US Classification:
428646, 428610, 428673, 428674, 22818022, 22818021, 228 563, 257772, 257E23023, 257E23028, 420560, 420557
Abstract:
Techniques and structures have been developed for providing lead-free column grid array interconnect structures. An exemplary interconnect has a body, a first joint, and a second joint, all having compositions off the eutectic composition in a ternary alloy system, the first joint having a ternary composition distinct from the body composition, and the second joint having a ternary composition distinct from the body composition and the first joint composition. The interconnect may be formed by solidifying a solder, having a Sn-poor ternary composition in the Sn—Ag—Cu alloy system, in contact with a column, having a Ag-rich Cu-deficient composition in the same system, and a bonding pad or bare substrate. A second solder, having a Sn-rich ternary composition, may be solidified in contact with the column and a second bonding pad or bare substrate. In some embodiments joints may be severed and reformed by remelting and resolidifying the lower-liquidus solder.

Isbn (Books And Publications)

Derivatives for Decision Makers: Strategic Management Issues

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Author

Bidyut C. Sen

ISBN #

0471129941

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Bidyut K Sen from Milpitas, CA, age ~67 Get Report