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Bing Fong Ma

from Sunnyvale, CA
Age ~68
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Also known as:
Bing F Ma, Bing C Ma, Fong Ma Bing, Bingfong Ma, Bing Fma, Bing Fong, G Ma, Ma Bing, Ing-Fong B Ma
Phone and address:
1117 Lillick Dr, Sunnyvale, CA 94087
(408) 243-1709
Related to:
Judith O'Connor, 86Richard O'Connor, 88Frederick R O'Connor, 88Lisa O'Connor, 56
Connected to:
Amartinez M Ma, 41Anastacia G Ma, 44Anemona L Ma, 54Angelita I Ma, 50Antonette G Ma, 38Asela M Ma, 69Atto Ma, 61Ayesha C Ma, 64Baofeng Ma, 50Baoju Ma, 37

Bing Ma Phones & Addresses

  • 1117 Lillick Dr, Sunnyvale, CA 94087 (408) 243-1709
  • San Francisco, CA

Resumes

Resumes

Bing Ma Photo 1

Bing Ma

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Semtech Corporation – Gennum Products
Principal Engineer
Bing Ma Photo 2

Senior Software Director

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Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
S3 Graphics Apr 2000 - Aug 2016
Senior Software Director
Huawei Technologies Apr 2000 - Aug 2016
Senior Software Director
Education:
Tsinghua University 1989 - 1998
Doctorates, Doctor of Philosophy, Philosophy, Mechanical Engineering
Skills:
Perl
Soc
Gpu
Computer Architecture
Processors
C
Embedded Systems
Device Drivers
Asic
Directx
C++
Opengl Es
Debugging
Arm
Linux
Opengl
Verilog
Gpgpu
H.264
Operating Systems
Direct3D
Testing
Graphics Processing Unit
Arm Architecture
Bing Ma Photo 3

Staff Engineer At Perkinelmer, Inc

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Location:
Santa Clara, CA
Industry:
Biotechnology
Work:
Varex Imaging Corporation
Staff Engineer
Perkinelmer, Inc.
Staff Engineer at Perkinelmer, Inc
Perkinelmer, Inc.
Process Integration Engineer
Education:
University of California, Berkeley
Skills:
Design of Experiments
Validation
Continuous Improvement
Semiconductors
Fda
Spc
Medical Devices
R&D

Business Records

Name / Title
Company / Classification
Phones & Addresses
Bing Ma
President
MLT ARCHITECTS ASSOCIATES, INC
456 Montgomery St STE 1410, San Francisco, CA 94104

Publications

Us Patents

Synchronous Rectifier For Boost Converters

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US Patent:
59948825, Nov 30, 1999
Filed:
Nov 3, 1998
Appl. No.:
9/185144
Inventors:
Bing Fong Ma - Sunnyvale CA
Assignee:
Linear Technology Corporation - Milpitas CA
International Classification:
G05F 110
US Classification:
323222
Abstract:
A boost DC-DC converter with a synchronous composite rectifier is presented. The boost DC-DC converter limits inductive in-rush current, includes a shutdown mode, operates also in step-down mode, and can be fabricated using conventional bipolar processes. The composite rectifier includes a power NPN transistor and a lateral PNP transistor. During converter start-up and in step-down mode (when the output voltage is less than the input voltage), the lateral PNP transistor drives the power NPN transistor. The lateral PNP transistor is biased such that inductive volt-second balance can be maintained, limiting in-rush current. In boost mode (when the output voltage is higher than the input voltage), the lateral PNP transistor is disabled and the power transistor is driven into saturation. Again, inductive volt-second balance can be maintained.

Power Mosfet Driver With Cross-Conduction Current Reduction

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US Patent:
52818624, Jan 25, 1994
Filed:
Oct 13, 1992
Appl. No.:
7/960246
Inventors:
Bing F. Ma - Sunnyvale CA
Assignee:
Micro Linear Corporation - San Jose CA
International Classification:
H03K 1760
H03K 512
US Classification:
307270
Abstract:
An output circuit includes a totem-pole output circuit for driving a power MOSFET. A pull-up circuit and a pull-down circuit drive the output node low or high as required. The circuit prevents the pull-up and pull-down circuits from simultaneously conducting current. The pull-up circuit has a pull-up threshold voltage and the pull-down circuit has a pull-down threshold voltage such that the pull-up circuit is turned off before the pull-down circuit is activated when the output node is switched from a high state to a low state and further wherein the pull-down circuit is turned off before the pull-up circuit is activated when the output node switches from a low state to a high state. The pull-up circuit is held off when the output node is switched from a high state to a low state by two diodes from the output node to an input of the pull-up circuit. The diodes are connected in series, one diode having its anode coupled to the output node and the cathode of the other diode coupled to the input of pull-up circuit.

Totem Pole Circuit With Additional Diode Coupling

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US Patent:
50234811, Jun 11, 1991
Filed:
Dec 27, 1989
Appl. No.:
7/457457
Inventors:
John Tero - Saratoga CA
Shaoan Chin - Cupertino CA
Bing F. Ma - Sunnyvale CA
Assignee:
North American Philips Corporation - New York NY
International Classification:
H03K 19088
H03K 19084
H03K 19013
H03K 1704
US Classification:
307456
Abstract:
An output circuit having the output taken between a pull-up output transistor and a pull-down output transistor connected in series for conducting current alternatively. Separate pull-up and pull-down driver circuits are controlled by a common input signal. The pull-down driver circuit is supplied by a pull-down current source, and a diode is connected from the point between the pull-down driver transistor and pull-down current source to the output node. The effect of a large node capacitance is reduced by the diode, which conducts current from the pull-down current source to any output load capacitance to raise the output voltage more rapidly when the pull-down driver circuit is cut off.

Micro Power R-C Relaxation Oscillator

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US Patent:
54185025, May 23, 1995
Filed:
Mar 3, 1994
Appl. No.:
8/205621
Inventors:
Bing F. Ma - Sunnyvale CA
W. Richard Davis - Sunnyvale CA
Assignee:
Micro Linear Corporation - San Jose CA
International Classification:
H03K 3023
H03K 3282
US Classification:
331111
Abstract:
An R-C relaxation oscillator having two comparators and a silicon controlled rectifier dissipates very low average power without resulting in frequency instabilities due to circuit propagation delays. A timing capacitor C. sub. T is charged through a timing resistor R. sub. T. The first comparator compares the voltage across the timing capacitor with an upper threshold voltage V. sub. TH. When the voltage across the timing capacitor crosses the upper threshold voltage, the comparator turns on the silicon controlled rectifier, which causes the capacitor to discharge the voltage that it has stored. The second comparator turns off the silicon controlled rectifier when the voltage across the timing capacitor falls below a lower threshold voltage V. sub. TL. The silicon controlled rectifier also provides boosted comparator bias current during the discharge phase, enabling the second comparator to respond quickly to the lower threshold voltage crossing and allowing fast capacitor discharge (therefore narrow clock pulses) and increasing frequency stability.
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Bing Fong Ma from Sunnyvale, CA, age ~68 Get Report