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Bishop C Brock

from Coupland, TX
Age ~66
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Also known as:
Bishop Chapman Brock, Bishop Rahelina Brock, Brock Chapman Bishop, Bishp C Brock, Brock Noname
Phone and address:
12306 Mccurry Rd, Beyersville, TX 78615
(512) 281-3928
Related to:
C Brock, 66Amy L Brock, 40Bevin B Brock, 63Nancy L Brock, 65Rahelina E Razanadrafara, 65Beverly H WilliamsC C BrockCraig A Brock, 42Brock Noname, 67
Connected to:
Alexa R Brock, 30Andre Brock, 44Angelika C Brock, 75Baine S Brock, 42Bantum Brock, 98Bertrand E Brock, 92Blayne L Brock, 39Bryce A Brock, 30Candie A Brock, 73Carolea Brock, 66

Bishop Brock Phones & Addresses

  • 12306 Mccurry Rd, Coupland, TX 78615 (512) 281-3928
  • 1911 36Th St, Austin, TX 78731 (512) 302-9139
  • Georgetown, TX
  • Travis, TX
  • Dallas, TX
  • Harriman, NY
  • Scottsdale, AZ
  • 12306 Mccurry Rd, Coupland, TX 78615 (512) 431-1542

Work

Position: Farmer

Education

Degree: Associate degree or higher

Emails

b***[email protected]

Resumes

Resumes

Bishop Brock Photo 1

Vice President And Research Staff Member

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Location:
15 Polk Ct, North Potomac, MD 20878
Industry:
Financial Services
Work:
A Major Financial Services Company
Vice President and Research Staff Member
Ibm Apr 2008 - Aug 2014
Senior Scientist, Ibm Power Systems Microprocessor Development
Ibm Aug 1997 - Aug 2004
Research Staff Member
Computational Logic Jan 1988 - May 1996
Computing Research Scientist
Education:
The University of Texas at Austin
Bachelors, Bachelor of Science, Chemistry The University of Texas at Austin
Bachelors, Bachelor of Arts, Computer Science The University of Texas at Austin
Master of Science, Masters, Computer Science
Skills:
C
Tcl/Tk
Lisp
Powerpc
Power Management
Rtos
Formal Verification
Formal Methods
Acl2
Full System Simulation
Embedded Systems
Logic Simulation
Functional Verification
Simics
Logic Design
Fpga Prototyping
Linux Kernel
Fault Simulation
Python
Technical Leadership
Vhdl
C++
Perl
Unix
Distributed Systems
Operating Systems
Servers
Computer Architecture
Hardware Architecture
Board Development
Prolog
Java
Jini
Vba
Windows System Programming
Simulations
Microprocessors
Firmware
Eda
Hardware
Debugging
System Architecture
Device Drivers
Algorithms
Tcl
Languages:
French
Bishop Brock Photo 2

Research Professional

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Location:
Austin, Texas Area
Industry:
Research

Publications

Us Patents

Interconnected Processing Nodes Configurable As At Least One Non-Uniform Memory Access (Numa) Data Processing System

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US Patent:
6421775, Jul 16, 2002
Filed:
Jun 17, 1999
Appl. No.:
09/335301
Inventors:
Bishop Chapman Brock - Austin TX
David Brian Glasco - Austin TX
James Lyle Peterson - Austin TX
Ramakrishnan Rajamony - Austin TX
Ronald Lynn Rockhold - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 15177
US Classification:
713 1, 713 2, 712 28, 709100
Abstract:
A data processing system includes a plurality of processing nodes that each contain at least one processor and data storage. The plurality of processing nodes are coupled together by a system interconnect. The data processing system further includes a configuration utility residing in data storage within at least one of the plurality of processing nodes. The configuration utility selectively configures the plurality of processing nodes into either a single non-uniform memory access (NUMA) system or into multiple independent data processing systems through communication via the system interconnect.

Operating System Support For In-Server Caching Of Documents

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US Patent:
6442654, Aug 27, 2002
Filed:
Dec 10, 1999
Appl. No.:
09/458406
Inventors:
Bishop Chapman Brock - Austin TX
Eli Chiprout - Austin TX
Elmootazbellah Nabil Elnozahy - Austin TX
Ramakrishnan Rajamony - Austin TX
Ronald Lynn Rockhold - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
US Classification:
711141, 711130, 711144, 711160
Abstract:
A system and method for providing in-server caching of shared data involves a server program that defines a server cache in RAM of a server machine and stores a selected file in the server cache. If a cached file is modified through the file system interface of the operating system of the server machine, the operating system automatically issues an upcall to the server program, the upcall identifying the modified file. In response to receipt of the upcall, the server program removes the modified file from the server cache. In one embodiment, the server program responds to a client request requiring access to a requested file by obtaining the requested file from the server cache if the server cache contains that file. Otherwise, the server program calls the operating system to obtain the requested file and then adds that file to the server cache as a cached file. The server program then generates a result based on the requested file and transmits the result to the remote data processing system.

System For Dynamically Adjusting Image Quality For Interactive Graphics Applications

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US Patent:
6473085, Oct 29, 2002
Filed:
Dec 17, 1999
Appl. No.:
09/465295
Inventors:
Bishop Chapman Brock - Austin TX
Eli Chiprout - Austin TX
Ramakrishnan Rajamony - Austin TX
Ronald Lynn Rockhold - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1516
US Classification:
345502, 345418, 709105
Abstract:
A method and system for optimizing image quality while operating an interactive graphics application within a data processing system. First, the image rendering speed for each of the rendering modes available within the interactive graphics application are assessed. Upon initial operation of the interactive graphics system, a default rendering mode is activated. During operation of the interactive graphics application, the processing load imposed on the data processing system is monitored and utilized as a user activity metric. The active rendering mode is updated in accordance with the user activity metric, such that the speed of the selected rendering mode varies inversely with the current processing load.

Efficient Identification Of Candidate Pages And Dynamic Response In A Numa Computer

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US Patent:
6499028, Dec 24, 2002
Filed:
Mar 31, 1999
Appl. No.:
09/282625
Inventors:
Bishop Chapman Brock - Austin TX
Eli Chiprout - Austin TX
Elmootazbellah Nabil Elnozahy - Austin TX
David Brian Glasco - Austin TX
Ramakrishnan Rajamony - Austin TX
Ronald Lynn Rockhold - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1700
US Classification:
707 4, 714 47, 709249
Abstract:
A performance monitor configured to count memory transactions and to issue an interrupt to the computer system if the monitor detects a specified number of transactions associated with a particular segment of the physical address space of the system. The monitor includes an interface suitable for coupling to an interconnect network of a computer system and configured to extract physical address information from a transaction traversing the interconnect network, a translation module adapted for associating the extracted physical address with one of a plurality of memory blocks and, in response thereto, incrementing a memory block counter corresponding to the memory block, and an interrupt unit configured to assert an interrupt if the block counter exceeds a predetermined value. The interface unit is configurable to selectively monitor either incoming or outgoing transactions and the translation unit preferably includes a plurality of region filters each comprising one or more of the memory blocks. In the preferred embodiment, the plurality of block counters are implemented with a random access memory device.

Memory Transaction Monitoring System And User Interface

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US Patent:
6601149, Jul 29, 2003
Filed:
Dec 14, 1999
Appl. No.:
09/460831
Inventors:
Bishop Chapman Brock - Austin TX
Eli Chiprout - Austin TX
Elmootazbellah Nabil Elnozahy - Austin TX
Ramakrishnan Rajamony - Austin TX
Ronald Lynn Rockhold - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
711154
Abstract:
A system for and method of monitoring memory transactions in a data processing system are disclosed. The method includes defining a set of memory transaction attributes with a monitoring system and detecting, on a data processing system connected to the monitoring system, memory transactions that match the defined set of memory transaction attributes. The number of detected memory transactions occurring during a specified duration are then displayed in a graphical format. In one embodiment, the data processing system comprises a non-uniform memory architecture (NUMA) system comprising a set of nodes. In this embodiment, the detected transactions comprise transactions passing through a switch connecting the nodes of the NUMA system. The set of memory transaction attributes may include memory transaction type information, node information, and transaction direction information. The data processing system may operate under a first operating system such as a Unix based system while the monitoring system operates under a second operating system such as a Windows operating system.

Selective Targeting Of Transactions To Devices On A Shared Bus

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US Patent:
6662251, Dec 9, 2003
Filed:
Mar 26, 2001
Appl. No.:
09/817089
Inventors:
Bishop Chapman Brock - Coupland TX
Gary Dale Carpenter - Pflugerville TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
710110, 709208
Abstract:
A system in which bus signals are selectively modified to effectively isolate desired bus agents from the bus. The selective modification of bus signals may be determined from a stored table (permission table) indicating permitted and prohibited bus transaction initiator/target pairs. The permission table may be located in a dedicated device, such as a programmable logic array or application specific integrated circuit. Alternatively, the permission table may be integrated into the bus arbiter. The permission table may be used to provide a unique 1-bit signal to each bus agent indicating whether the corresponding bus agent is permitted to receive transactions from the current bus master. The permission bit may be routed to external gating circuitry associated with each bus agent. The gating circuitry may receive one or more bus control signals and may modify the control signals depending upon the state of the permission bit. In an embodiment in which the bus is a PCI bus, the gating circuitry may receive the FRAME# and GNT# signals for each bus agent.

Method And Apparatus For Controlling Power And Performance In A Multiprocessing System According To Customer Level Operational Requirements

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US Patent:
6836849, Dec 28, 2004
Filed:
Apr 5, 2001
Appl. No.:
09/826986
Inventors:
Bishop Chapman Brock - Coupland TX
Harm Peter Hofstee - Austin TX
Mark A. Johnson - Austin TX
Kevin John Nowka - Round Rock TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 126
US Classification:
713310, 713300, 713320, 713322, 713323, 713324, 713340
Abstract:
A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system.

System And Method For Controlling A Multiplexer For Selecting Between An Input Clock And An Input Duty-Cycle-Corrected Clock And Outputting The Selected Clock And An Enable Signal

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US Patent:
6886106, Apr 26, 2005
Filed:
Oct 16, 2001
Appl. No.:
09/978358
Inventors:
Bishop Chapman Brock - Coupland TX, US
Gary Dale Carpenter - Pflugerville TX, US
Amanda Christine Caswell - Austin TX, US
Eric William MacDonald - Cedar Park TX, US
Timothy Joe Rubidoux - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F001/04
G06F001/32
H03K003/017
US Classification:
713500, 713322, 327175
Abstract:
A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the width of the input clock cycle, that is asserted one or two input clock cycles prior to the rising edge alignment of the input and output clocks, that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.
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Bishop C Brock from Coupland, TX, age ~66 Get Report