Bo Lay Tang

7088144, Aug 8, 2006

Sep 10, 2004

10/937985

Bo Tang - Fremont CA, US
Edgardo F. Klass - Palo Alto CA, US
Geoffrey M. Pilling - Santa Clara CA, US

Sun Microsystems, Inc. - Santa Clara CA

H03K 19/20
H03K 19/082
H03K 19/00
H03K 19/096

326119, 326 93, 326 94, 326 95, 326 96, 326 97, 326 98, 326112, 326121

A method and apparatus for creating a modified dynamic flip-flop avoids the power waste created by prior art dynamic flip-flops by including a conditional pre-charge control circuit and method. When the modified dynamic flip-flop is in a holding mode, i. e. , in the clock disable state, the modified dynamic flip-flop does not use power pre-charging and discharging the internal dynamic node every cycle.

7629815, Dec 8, 2009

Jul 25, 2008

12/180441

Bo Tang - Sunnyvale CA, US
Ilyas Elkin - Sunnyvale CA, US
Georgios K. Konstadinidis - Santa Clara CA, US

Sun Microsystems, Inc. - Santa Clara CA

H03K 19/20

326121, 326 93, 326 46

A modified high-speed flip-flop including an input circuit, a smart window circuit, a smart keeper circuit, a pre-charge circuit, a discharge circuit, a slave storage circuit, and an output circuit. Additionally, a circuit including the modified high-speed flip-flop, the circuit also including a non-zero operating voltage provided to the flip-flop, a common voltage provided to the flip-flop, a clock signal input to the flip-flop, a data signal input to the flip-flop wherein the data signal has a high state and a low state, and an output signal from the flip-flop wherein the output signal has a high state and a low state.

7843244, Nov 30, 2010

Jul 2, 2009

12/497027

Bo Tang - Cupertino CA, US
Edgardo F. Klass - Cupertino CA, US

Apple Inc. - Cupertino CA

H03K 3/289

327202, 327203

A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal.

7977976, Jul 12, 2011

May 21, 2010

12/784751

Bo Tang - Sunnyvale CA, US
Edgardo F. Klass - Palo Alto CA, US

Apple Inc. - Cupertino CA

H03K 19/00

326 94, 326 93, 326 95, 326 96

A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the first latch may enter into a metastable, or undefined logic state. A second latch may remain stable, and store a previous value corresponding to data that has most recently been transferred from the source clock domain to the target clock domain. The respective values output by the two latches may be compared by a detection circuit, and a value derived from the output value of the first latch and corresponding to the current data may be written to an output latch if the current data differs from the stored previous value. The detection circuit may also provide a defined logical value to the output latch even if the first latch is in a metastable state.

8134387, Mar 13, 2012

Jun 2, 2011

13/151700

Bo Tang - Sunnyvale CA, US
Edgardo F. Klass - Palo Alto CA, US

Apple Inc. - Cupertino CA

H03K 19/00

326 94, 326 93, 326 95, 326 98

A synchronizer circuit for transferring data from a source clock domain to a target clock domain. A first latch in the target clock domain may capture a data value corresponding to current data received from the source clock domain. Under certain conditions, the first latch may enter into a metastable, or undefined logic state. A second latch may remain stable, and store a previous value corresponding to data that has most recently been transferred from the source clock domain to the target clock domain. The respective values output by the two latches may be compared by a detection circuit, and a value derived from the output value of the first latch and corresponding to the current data may be written to an output latch if the current data differs from the stored previous value. The detection circuit may also provide a defined logical value to the output latch even if the first latch is in a metastable state.

8181074, May 15, 2012

Dec 20, 2007

11/961952

Bo Tang - Sunnyvale CA, US

Oracle America, Inc. - Redwood City CA

H03K 19/003

714746, 326 13, 327208, 327212

A soft error recoverable storage element suitable for use in latches, flip-flops, static ram memory cells and microprocessor pipeline stages. The storage element employs a redundant copy of the stored data value and a feedback loop. One embodiment employs an interlocking four inverter loop with gating devices that blocks the propagation of a soft error induced change of state and causes the storage element to recover its original stored data state.

8305125, Nov 6, 2012

Oct 14, 2010

12/904340

Bo Tang - Cupertino CA, US
Edgardo F. Klass - Cupertino CA, US

Apple Inc. - Cupertino CA

H03K 3/289

327202, 327203

A synchronizer circuit includes a master stage and a slave stage. The master stage may include a first master latch coupled to receive a data input signal, and a clock signal. The master stage may also include a second master latch coupled to receive the data input signal, and a delayed version of the clock signal. The master stage may further include a pull-up circuit that may drive an output line of the master stage depending upon an output of each of the first master latch and the second master latch. The slave stage may include a slave latch having an input coupled to the output line of the master stage. The slave stage may provide an output data signal that corresponds to the captured input data signal and is synchronized to the receiving clock signal.

8332698, Dec 11, 2012

May 21, 2010

12/784748

Bo Tang - Sunnyvale CA, US
Edgardo F. Klass - Palo Alto CA, US

Apple Inc. - Cupertino CA

G01R 31/28

714726

A number of scan flops clocked by a master clock may be used to constructing a scan chain to perform scan tests. During a scan test, data appearing at the regular data input of each scan flop may be written into a master latch of the scan flop during a time period when the scan control signal is in a state corresponding to a capture cycle. A slave latch in each scan flop may latch a value appearing at the regular data input of the scan flop according to a narrow pulse triggered by the rising edge of the master clock when the scan control signal is in the state corresponding to the capture cycle. The slave latch may latch the data provided by the master latch according to a wide pulse triggered by the rising edge of the master clock when the scan control signal is in a state corresponding to a shift cycle. This may permit toggling the scan control signal during either a high phase or a low phase of the master clock, and may also enable testing the pulse functionality of each scan flop.