Resumes
Resumes
Charles Laverty Phones & Addresses
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8408 Mendocino Dr NE, Albuquerque, NM 87122
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4905 Skyline Ridge Ct NE, Albuquerque, NM 87111
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Ranchos de Taos, NM
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Las Cruces, NM
Publications
Us Patents
Method And Apparatus For Distributing Clock Signals
View pageUS Patent:
8350590, Jan 8, 2013
Filed:
Jan 27, 2010
Appl. No.:
12/694973
Inventors:
Schuyler E. Shimanek - Albuquerque NM, US
Wayne E. Wennekamp - Rio Rancho NM, US
Charles D. Laverty - Albuquerque NM, US
John O'Dwyer - Maynooth, IE
Wayne E. Wennekamp - Rio Rancho NM, US
Charles D. Laverty - Albuquerque NM, US
John O'Dwyer - Maynooth, IE
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/173
G06F 1/04
G06F 1/04
US Classification:
326 38, 326 93, 713501, 713400
Abstract:
A technique is provided that involves: configuring a clock generation circuit to output a first signal having a first frequency that is one of a plurality of frequencies that are different; generating in a clock section of a further circuit as a function of the first signal a second signal having a second frequency that is one of the plurality of frequencies other than the first frequency; and configuring the clock section to supply to the further circuit a clock signal that is one of the first and second signals.
Apparatus And Method For Memory Cell Power-Up Sequence
View pageUS Patent:
7782702, Aug 24, 2010
Filed:
Oct 3, 2008
Appl. No.:
12/245144
Inventors:
Eric E. Edwards - Albuquerque NM, US
Charles D. Laverty - Albuquerque NM, US
Charles D. Laverty - Albuquerque NM, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G11C 5/14
US Classification:
365226, 365228, 365229, 365206
Abstract:
A method and apparatus is provided to enhance the power-up sequence for integrated circuits (ICs) that contain memory cells having single-ended data inputs with no local reset function. During a power-up sequence, the logic levels that are applied to the data, address, and power inputs of the memory cell are restricted to particular magnitudes by a power-on reset (POR) state machine. First, the data input of the memory cell is held to a logic low value while an address signal of the memory cell is allowed to be asserted to a logic high value in conjunction with activating a power supply that provides operational power to the IC. Next, the address input to the memory cell ramps up to full logic high value, while the regulated power supply to the memory cell array is held low. The regulated power supply then ramps up to an operational level to bias the memory cell into a known logic state.