Chenmin H Hu

20120259574, Oct 11, 2012

Apr 5, 2011

13/080474

Chenmin Hu - Santa Clara CA, US
Bo Su - San Jose CA, US
Ping Zhang - Saratoga CA, US
Yuan Xu - Sunnyvale CA, US
Qing Zhang - Shanghai, CN

G06F 19/00

702117

An integrated-circuit yield improvement system includes a global signature analysis/grouping module configured to receive an integrated circuit (IC) design and identify areas in the IC design that include potential defect signatures based on the defect signatures stored in the defect signature library. The global signature analysis/grouping module can produce a global signature map indicating these areas and their associated potential defect signatures in the IC design. A local signature analysis/grouping module can identify and group local defect signatures in the IC design with the process monitoring and yield data as input, to output grouped local signatures. An intelligent learning engine can analyze the global signature map and the grouped local signatures and update some of the defect signatures in the defect signature library. A feedback loop is formed to update and renew the contents of the defect signature library for each new IC design while process and yield are improved.

20180033132, Feb 1, 2018

Sep 20, 2017

15/709856

- San Clara CA, US
Chenmin Hu - Saratoga CA, US
Ye Chen - San Jose CA, US
Yue Ma - San Jose CA, US
Chingyun Hsiang - Cupertino CA, US
Justin Chen - Milpitas CA, US
Raymond Xu - Sunnyvale CA, US
Abhishek Vikram - Santa Clara CA, US
Ping Zhang - Saratoga CA, US

G06T 7/00
G06K 9/46
G06K 9/52
G06K 9/62

Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.

20160300338, Oct 13, 2016

Mar 10, 2016

15/066280

- Santa Clara CA, US
Chenmin Hu - Saratoga CA, US
Ye Chen - San Jose CA, US
Yue Ma - San Jose CA, US
Chingyun Hsiang - Cupertino CA, US
Justin Chen - Milpitas CA, US
Raymond Xu - Sunnyvale CA, US
Abhishek Vikram - Santa Clara CA, US
Ping Zhang - Saratoga CA, US

G06T 7/00
G06K 9/52
G06T 7/60
G06K 9/46
G06K 9/62

Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.