Search

Darel N Emmot

from Fort Collins, CO
Age ~65
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Also known as:
Darel Emmot Neal
Phone and address:
137 2Nd St, Fort Collins, CO 80524
(970) 231-5911
Related to:
Sidney D Terry, 87Elizabeth A Terry, 58Steven L Ferrell, 62Cynthia K Emmot, 67William J Ferrell, 86Timothy M Jean, 59Mary C Ferrell, 72Shean R Ferrell, 49
Connected to:
Douglas W Emmot, 77Ronald P Emmot, 70Dana L Emmott, 68Lisa A Emmott, 64Marian M Emmott, 100Matthew T Emmott, 54Jon Emmrich, 56Helen L Emms, 75Raymond Emms, 69Steven R Emms, 44

Darel Emmot Phones & Addresses

  • 137 2Nd St, Fort Collins, CO 80524 (970) 231-5911
  • 5524 County Road 11, Fort Collins, CO 80524 (970) 416-7315
  • 5524 Turnberry Rd, Fort Collins, CO 80524 (970) 416-7315
  • Wellington, CO

Work

Company: Hewlett-packard Aug 2015 to Aug 2012 Position: Master engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: Kansas State University 1984 to 1988

Skills

Analytic Modeling • Root Cause Problem Solving • Computer Performance • Queuing • Memory • Computer Architecture • Processors • Vlsi • Cache Coherency • Logic Design • Combinatorics • Mathematics • Perl • Asic • High Performance Computing • Debugging • System Architecture

Industries

Information Technology And Services

Resumes

Resumes

Darel Emmot Photo 1

Darel Emmot

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Location:
137 2Nd St, Fort Collins, CO 80550
Industry:
Information Technology And Services
Work:
Hewlett-Packard Aug 2015 - Aug 2012
Master Engineer
Education:
Kansas State University 1984 - 1988
Bachelors, Bachelor of Science Kansas State University 1977 - 1981
Bachelors, Bachelor of Science, Electronics Engineering
Skills:
Analytic Modeling
Root Cause Problem Solving
Computer Performance
Queuing
Memory
Computer Architecture
Processors
Vlsi
Cache Coherency
Logic Design
Combinatorics
Mathematics
Perl
Asic
High Performance Computing
Debugging
System Architecture

Publications

Us Patents

Modified Aggressive Precharge Dram Controller

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US Patent:
6470433, Oct 22, 2002
Filed:
Apr 29, 2000
Appl. No.:
09/562600
Inventors:
Bryan G Prouty - Wellington CO
Darel N Emmot - Ft Collins CO
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1200
US Classification:
711168, 711105, 711151, 711170
Abstract:
A modified aggressive precharge method and apparatus for controlling a DRAM or system of DRAMs. Groups of memory access commands are sent to a DRAM controller. A bank/row activate command indicator is associated with the beginning of each group, and a bank precharge command indicator is associated with the end of each group. Normally, the DRAM controller will close the bank/row corresponding to a group responsive to the bank precharge command indicator associated with the end of the group; but the DRAM controller may conditionally leave the bank/row open, as follows: The DRAM controller analyzes the command stream to determine whether first and second groups of memory access commands are directed to the same row and bank. If so, then the precharge command indicated at the end of the first group and the activate command indicated at the beginning of the second group are not executed. The effect is to leave the bank/row of the first group open so that the second group may access it without having to reopen it.

Z Test And Conditional Merger Of Colliding Pixels During Batch Building

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US Patent:
6559852, May 6, 2003
Filed:
Jul 31, 1999
Appl. No.:
09/364972
Inventors:
Jon L Ashburn - Fort Collins CO
Darel N Emmot - Ft Collins CO
Byron A Alcorn - Ft Collins CO
Assignee:
Hewlett Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1328
US Classification:
345533, 345422, 345570, 345503, 710112, 710310
Abstract:
Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be âtossedâ and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixels BEN. The buffered BEN may be replaced with the logical OR of the stored BEN and the incoming pixels BEN.

Window Copy-Swap Using Multi-Buffer Hardware Support

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US Patent:
6587112, Jul 1, 2003
Filed:
Jul 10, 2000
Appl. No.:
09/613229
Inventors:
Courtney Goeltzenleuchter - Fort Collins CO
Darel N Emmot - Ft Collins CO
Jon L Ashburn - Fort Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06T 100
US Classification:
345532
Abstract:
A 3D graphics controller configurable to simultaneously copy portions of a pixel region between a back buffer and a front buffer. The 3D graphics controller includes four memory controllers, each controlling a bank of frame buffer memory. A sequence of addresses defining a pixel region is generated. The addresses are distributed to the four memory controllers according to the memory banks (addresses) coupled thereto. Each memory controller is configured to read pixels according to the addresses and a first offset; and write the pixels according to the addresses and a second offset. The offsets are chosen so as not to shift pixels within the banks. Therefore, each memory controller simultaneously and independently copies a portion of the pixel region without accessing any other memory banks resulting in a copy of the entire pixel region.

Managing Texture Mapping Data In A Computer Graphics System

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US Patent:
6636225, Oct 21, 2003
Filed:
Aug 27, 2001
Appl. No.:
09/940039
Inventors:
Byron A. Alcorn - Fort Collins CO
Darel N. Emmot - Fort Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06T 1140
US Classification:
345552, 345538, 345587
Abstract:
A method and apparatus for managing texture mapping data in a computer graphics system, the computer graphics system including a host computer, primitive rendering hardware and a primitive data path extending between the host computer and the primitive rendering hardware. The host computer passes primitives to be rendered by the system to the primitive rendering hardware over the primitive data path. The host computer has a main memory that stores texture mapping data corresponding to the primitives to be rendered. The primitive rendering hardware includes a local texture memory that locally stores the texture mapping data corresponding to at least one of the primitives to be rendered. When a primitive passed to the primitive rendering hardware is to be rendered, a determination is made as to whether its corresponding texture mapping data is in the local texture memory. When the texture mapping data corresponding to the primitive to be rendered is in the local texture memory, the primitive is rendered using its corresponding texture mapping data from the local texture memory. When the texture mapping data corresponding to the primitive to be rendered is not in the local texture memory, the texture mapping data corresponding to the primitive to be rendered is downloaded from the host computer main memory to the primitive rendering hardware, and the primitive is rendered using its corresponding texture mapping data downloaded from the main memory.

Unified Memory Distributed Across Multiple Nodes In A Computer Graphics System

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US Patent:
6657632, Dec 2, 2003
Filed:
Jan 24, 2001
Appl. No.:
09/768664
Inventors:
Darel N Emmot - Ft Collins CO
Byron A Alcorn - Ft Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1516
US Classification:
345502, 345505, 345506, 711118, 712 10, 712 11
Abstract:
A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Anti-Aliasing In A Computer Graphics System Using A Texture Mapping Subsystem To Down-Sample Super-Sampled Images

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US Patent:
6661424, Dec 9, 2003
Filed:
Jul 7, 2000
Appl. No.:
09/611503
Inventors:
Byron A Alcorn - Ft Collins CO
Darel N Emmot - Ft Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G09G 500
US Classification:
345611, 345581
Abstract:
Methods and apparatus are provided for performing scene anti-aliasing in a computer graphics system including a rasterizer, a texture mapping subsystem and a frame buffer. The method includes the steps of defining a supersample image buffer and a single sample image buffer, using the rasterizer to render a supersampled image to the supersample image buffer, and using the texture mapping subsystem to downsample the supersample image to the single sample image buffer. The downsampled image in the single sample image buffer is anti-aliased. The supersample image buffer and the single sample image buffer are preferably allocated in the frame buffer. The downsampling operation is preferably performed at the time of double buffer swap.

Z Test And Conditional Merger Of Colliding Pixels During Batch Building

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US Patent:
6680737, Jan 20, 2004
Filed:
Dec 12, 2002
Appl. No.:
10/317526
Inventors:
Jon L Ashburn - Fort Collins CO
Darel N Emmot - Ft Collins CO
Byron A Alcorn - Ft Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G09G 539
US Classification:
345531, 345533, 345570, 345421, 710 39, 710 54, 710310
Abstract:
Frame buffer memory bandwidth is conserved by performing a depth comparison between colliding pixels at batch building time. If the incoming pixel fails the depth comparison, then it may be âtossedâ and excluded from any batches currently under construction. The batch building process may then continue without the need for a batch flush responsive to the occurrence of the pixel collision. If the incoming pixel passes the depth comparison, then it may yet be possible to avoid flushing: The current rendering mode of the pipeline is determined. If the current rendering mode does not require read-modify-write operations, then the incoming pixel may be merged with the buffered pixel with which it collides. Merger of the two pixels may be accomplished by overwriting the buffered RGBA pixel components with those of the incoming pixel, but only those components corresponding to asserted bits in the incoming pixels BEN. The buffered BEN may be replaced with the logical OR of the stored BEN and the incoming pixels BEN.

Graphics Data Storage In A Linearly Allocated Multi-Banked Memory

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US Patent:
6724396, Apr 20, 2004
Filed:
Jun 1, 2000
Appl. No.:
09/586412
Inventors:
Darel N Emmot - Ft Collins CO
Byron A Alcorn - Ft Collins CO
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G09G 500
US Classification:
345587, 345582
Abstract:
Methods and apparatus are provided for allocating correlated data sets, such as texture data, among first and second areas of memory in a computer graphics system. Each texture map in a series of texture maps is divided into a set of blocks of data. Each texture map that has a width greater than one block is divided into first and second map areas. Typically, the first and second map areas are the left and right halves of each texture map. Blocks of data from the first map areas of odd level texture maps are stored in the first memory area, blocks of data from the second map areas of even level texture maps are stored in the first memory area, blocks of data from the second map areas of odd level texture maps are stored in the second memory area and blocks of data from the first map areas of even level texture maps are stored in the second memory area. The blocks of data representing each texture map in the series of texture maps are stored in consecutive blocks of memory. The disclosed technique for allocating texture data to memory provides high performance during texture mapping operations.
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Darel N Emmot from Fort Collins, CO, age ~65 Get Report