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Wenwei Wang Phones & Addresses

  • Cupertino, CA
  • 177 Monroe St APT 6, Santa Clara, CA 95050
  • Sunnyvale, CA
  • San Jose, CA
  • Seattle, WA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Wenwei Wang
Proto Tree LLC
1900 Powell St, Oakland, CA 94608
2850 Octavia St, Oakland, CA 94619

Publications

Us Patents

Apparatus, System, And Method For Adjusting Memory Hold Time

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US Patent:
7987334, Jul 26, 2011
Filed:
Feb 28, 2008
Appl. No.:
12/039586
Inventors:
WenWei Wang - Gilroy CA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/02
US Classification:
711170
Abstract:
An apparatus, system, and method are disclosed for adjusting memory hold time. A detection module detects a hold time violation for a memory. An adjustment module increases a first voltage of a voltage controller in response to the hold time violation. The voltage controller supplies electrical current at the first voltage to a memory controller and at a reference voltage to the memory. The first and reference voltages are set independently.

Apparatus, System, And Method For Grounding Integrated Circuit Outputs

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US Patent:
20090219076, Sep 3, 2009
Filed:
Feb 28, 2008
Appl. No.:
12/039580
Inventors:
Wenwei Wang - Gilroy CA, US
International Classification:
H03K 17/687
US Classification:
327427
Abstract:
An apparatus, system, and method are disclosed for grounding IC outputs. A first switching module turns on when an IC power supply voltage exceeds a base voltage. The first switching module is in communication with IC outputs and a common ground. The IC outputs are configured to be pulled up to the IC power supply voltage through pull-up resistors when a first voltage is driven lower than the base voltage. In addition, the first switching module connects the IC outputs to the common ground. A second switching module turns on, turns turn off the first switching module, disconnects the IC outputs from the common ground, and pulls the IC outputs up to the IC power supply voltage when the IC power supply voltage exceeds a minimum working voltage.

Electrostatic Discharge Protection For Magneto-Resistive Heads

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US Patent:
61040487, Aug 15, 2000
Filed:
Jun 30, 1999
Appl. No.:
9/345038
Inventors:
Wenwei Wang - Fremont CA
Larry Trung Vo - San Jose CA
Assignee:
Iomega Corporation - Roy UT
International Classification:
H01L 2980
US Classification:
257272
Abstract:
An electrostatic protection network is disclosed that may be employed in a disk drive having a magneto-resistive read element. The network comprises a ground; and an array that block a signal current flow between the read element and the ground while a signal voltage is below a predetermined value and conducts the signal current from the read element to the ground while the signal voltage is above the predetermined value. The array is formed of a N-channel and P-channel junction field effect transistors. Thus, electrostatic discharge events are dissipated through the network to diminish damage to the read element during an ESD event.

Automated Power Noise Susceptibility Test System For Storage Device

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US Patent:
20220357781, Nov 10, 2022
Filed:
May 4, 2021
Appl. No.:
17/307157
Inventors:
- Gyeonggi-do, KR
Wenwei WANG - San Jose CA, US
Dean HOGLE - San Jose CA, US
International Classification:
G06F 1/26
H03F 3/45
G05F 1/46
H03K 5/1252
G06F 13/16
G06F 13/42
Abstract:
Automated power noise susceptibility test systems are provided for one or more storage devices. A system includes a host; storage devices; and multiple noise injection modules. Each noise injection module includes: a first relay to a third relay, which are coupled to a first path or a second path. The first path includes: an operational amplifier for generating a high noise function; a first variable regulator for generating a first or second regulated power supply voltage; and a capacitor injection circuit for generating low noise function and a first power noise. The second path includes: a second variable regulator for generating a third or fourth regulated power supply voltage and a power amplifier injection circuit for generating a second power noise. The third relay selectively provides the storage device the first power noise or the second power noise.

Storage Device With Detachable Capacitor Connection Structure

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US Patent:
20220231437, Jul 21, 2022
Filed:
Apr 5, 2022
Appl. No.:
17/713732
Inventors:
- Gyeonggi-do, KR
Danyang QIAO - Santa Clara CA, US
Wenwei WANG - San Jose CA, US
International Classification:
H01R 12/70
H05K 1/18
H01R 12/71
H01R 12/73
Abstract:
A detachable capacitor connection structure is provided for a storage device. In an embodiment, a connection element detachably connects a capacitor module including one or more capacitors to a circuit board such that the capacitor module is stacked over the circuit board. The connection element includes: a first connector including two pin headers, mounted on a bottom plane of the capacitor module; and a second connector including two sockets, mounted on a top plane of the circuit board corresponding to the bottom of the capacitor module, suitable for connecting the first connector to the circuit board.

Storage Device With Detachable Capacitor Connection Structure

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US Patent:
20210367360, Nov 25, 2021
Filed:
May 20, 2020
Appl. No.:
16/879521
Inventors:
- Gyeonggi-do, KR
Danyang QIAO - Santa Clara CA, US
Wenwei WANG - San Jose CA, US
International Classification:
H01R 12/70
H05K 1/18
H01R 12/71
H01R 12/73
Abstract:
A detachable capacitor connection structure is provided for a storage device. In an embodiment, a connection element detachably connects a capacitor module including one or more capacitors to a circuit board such that the capacitor module is stacked over the circuit board. The connection element includes: a first connector including two pin headers, mounted on a bottom plane of the capacitor module; and a second connector including two sockets, mounted on a top plane of the circuit board corresponding to the bottom of the capacitor module, suitable for connecting the first connector to the circuit board.

Noise Injection For Power Noise Susceptibility Test For Memory Systems

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US Patent:
20210304833, Sep 30, 2021
Filed:
Mar 30, 2020
Appl. No.:
16/834464
Inventors:
- Gyeonggi-do, KR
Wenwei WANG - San Jose CA, US
Satish PRATAPNENI - Milpitas CA, US
International Classification:
G11C 29/02
G01R 29/08
G01R 29/26
Abstract:
Noise injection systems and methods for conducting power noise susceptibility tests on memory systems, including solid state drives. A noise injection system comprises a power selector to deliver a voltage at a first or second level according to a frequency level indicated by a frequency select signal; a noise signal relay to receive a frequency noise signal and to deliver a low or high frequency noise component of the frequency noise signal according to the frequency level of the frequency select signal; and an amplification assembly, responsive to the frequency select signal and which receives the first or second level voltage based on the frequency level of the frequency select signal, receives and amplifies the high frequency noise component when the frequency select signal indicates a high frequency level, and receives and amplifies the low frequency noise component when the frequency select signal indicates a low frequency level.

Circuits And Methods Of Operating The Circuits

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US Patent:
20210265988, Aug 26, 2021
Filed:
Feb 25, 2020
Appl. No.:
16/800630
Inventors:
- Gyeonggi-do, KR
Wenwei WANG - San Jose CA, US
Danyang QIAO - Santa Clara CA, US
International Classification:
H03K 3/356
H03K 19/0185
Abstract:
Circuits integrating OR logic and level shifting functionality and methods of operating the same are configured to accommodate different applications. One such circuit comprises first and second transistors coupled in parallel defining first and second nodes, the first transistor being responsive to a first input signal and the second transistor being responsive to a second input signal; a first resistor coupled between a power supply terminal of the circuit and the first node; and a second resistor coupled between the second node and a ground terminal of the circuit. The circuit generates an output signal having a voltage level that is lower than a voltage level of each of the first and second input signals.
Wenwei D Wang from Cupertino, CA, age ~56 Get Report