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Dwight David Birdsall

from Fort Collins, CO
Age ~68
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Also known as:
Dwight D Birdsall, Denise Michele Birdsall, Denise Michelle Birdsall, Denise D Birdsall, Denise M Birdsall, Dwight B Birdsell
Phone and address:
2831 Blue Leaf Dr, Fort Collins, CO 80526
(970) 568-8886
Related to:
Mark Thomas, 44Denise M Birdsall, 64Zach D BirdsallZachary Birdsall, 40Stacey R Boskovich, 41Zach D Birdsall, 40Janaine R Boskovich, 63Kaitlyn Birdsall, 36
Connected to:
Bonnie S Birdsall, 67Chris Birdsall, 78Chrisana Birdsall, 54Clare T Birdsall, 28Consuelo Birdsall, 54Dawn A Birdsall, 65Gail S Birdsall, 59Gloria J Birdsall, 74Hiroko Birdsall, 88Jeannette T Birdsall, 93

Dwight Birdsall Phones & Addresses

  • 2831 Blue Leaf Dr, Fort Collins, CO 80526 (970) 568-8886
  • Beaver, UT
  • Norwalk, CA
  • 2831 Blue Leaf Dr, Fort Collins, CO 80526

Work

Company: Analog circuit works Aug 2017 Position: Senior design engineer

Skills

Mixed Signal • Analog • Semiconductors • Ic • Asic • Analog Circuit Design • Integrated Circuit Design • Cmos • Circuit Design • Rf • Soc • Cadence Virtuoso • Eda • Semiconductor Industry • Power Management • Debugging • Radio Frequency

Industries

Electrical/Electronic Manufacturing

Resumes

Resumes

Dwight Birdsall Photo 1

Senior Design Engineer

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Location:
Fort Collins, CO
Industry:
Electrical/Electronic Manufacturing
Work:
Analog Circuit Works
Senior Design Engineer
Maxim Integrated 2001 - Dec 2015
Principal Member of Technical Staff , Ic Design
Comlinear Corp National Semiconductor 1993 - 2001
Senior Member Technical Staff
Hughes Aircraft Company 1981 - 1993
Member of Technical Staff
Skills:
Mixed Signal
Analog
Semiconductors
Ic
Asic
Analog Circuit Design
Integrated Circuit Design
Cmos
Circuit Design
Rf
Soc
Cadence Virtuoso
Eda
Semiconductor Industry
Power Management
Debugging
Radio Frequency

Publications

Us Patents

Power-Efficient Sample And Hold Circuit Using Bipolar Transistors Of Single Conductivity Type

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US Patent:
53151690, May 24, 1994
Filed:
Jun 8, 1992
Appl. No.:
7/894980
Inventors:
Lloyd F. Linder - Agoura Hills CA
Benjamin Felder - Saugus CA
Dwight D. Birdsall - Norwalk CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H03K 524
H03K 1774
US Classification:
307353
Abstract:
A diode bridge includes a plurality of diodes for coupling an input voltage signal to a holding capacitor for sampling when the diodes are forward biased, and uncoupling the voltage signal from the capacitor for holding when the diodes are reverse biased. The diode bridge has first and second bias current nodes. A constant current drain causes a constant bias current to flow out of the bridge. A transistor connects the first node to the drain for forward biasing the diodes, whereas a transistor connects the second node to the drain for reverse biasing the diodes. A bootstrap amplifier (A2) produces a variable control voltage which controls a pair of voltage-controlled constant current sources to cause the constant bias current to flow therethrough into the bridge. A transistor (Q7) couples the control voltage to the first current source for forward biasing the diodes, whereas a transistor couples the control voltage to the second current source for reverse biasing the diodes. The transistors are all bipolar and of the same conductivity type, preferably NPN.

Single-Ended And Differential Transistor Amplifier Circuits With Full Signal Modulation Compensation Techniques Which Are Technology Independent

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US Patent:
52509117, Oct 5, 1993
Filed:
Apr 20, 1992
Appl. No.:
7/871861
Inventors:
Lloyd F. Linder - Agora Hills CA
Dwight D. Birdsall - Norwalk CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H03F 114
US Classification:
330149
Abstract:
A compensating transistor (Q5) is connected in series with the collector of a main transistor (Q3), and a level shifted replica (Vin+V1) of an input signal (Vin) is applied to the base of the compensating transistor (Q5) to maintain a constant voltage difference between the base and collector of the main transistor (Q3) and compensate for base width modulation. DELTA. Vce. A voltage-controlled current source (S1) is responsive to the input signal (Vin) and applies a compensating current. DELTA. Iload which is equal and opposite to the load current variation caused by a change (. DELTA. Vin) in the input voltage (Vin) to the emitter of the main transistor (Q3) to compensate for load current modulation. DELTA. Vbe. Alternatively, the compensating current can be applied to the junction of the base of the main transistor (Q3) and the emitter of pre-distortion transistor (Q4) which has a base connected to receive the input signal (Vin). Another compensating transistor (Q12) applies a current (. DELTA.

Transistor Current Switch Array For Digital-To-Analog Converter (Dac) Including Bias Current Compensation For Individual Transistor Current Gain And Thermally Induced Base-Emitter Voltage Drop Variation

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US Patent:
54831504, Jan 9, 1996
Filed:
Feb 5, 1993
Appl. No.:
8/017200
Inventors:
Phillip L. Elliott - Fort Collins CO
Dwight D. Birdsall - Norwalk CA
Lloyd F. Linder - Agora Hills CA
Kelvin T. Tran - Carson CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
G05F 308
US Classification:
323312
Abstract:
A bias voltage source (20) produces a variable bias voltage (VBREF) which regulates the bias currents in an array (30) of transistor current switch cells (34,36) in an digital-to-analog converter (DAC). The bias voltage (VBREF) is applied to the bases of the regulating transistors (Q8') in the cells (34,36) to regulate the bias currents in their respective main transistors (Q6',Q7') to values proportional to the main bias current (IBIAS). Each main transistor (Q6,Q6',Q7,Q7') and regulating transistor (Q8,Q8') is provided with a compensating transistor (Q10,Q10')(Q11,-Q11') which sinks the emitter-base current thereof and cancels deviation of the actual current gain from the design current gain. Another compensating transistor (Q9,Q9') is connected to each regulating transistor (Q8,Q8') to cancel the effect of base-emitter voltage variation with temperature.

Sample-And-Hold Circuit Including Push-Pull Transconductance Amplifier And Current Mirrors For Parallel Feed-Forward Slew Enhancement And Error Correction

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US Patent:
53789385, Jan 3, 1995
Filed:
Feb 5, 1993
Appl. No.:
8/018856
Inventors:
Dwight D. Birdsall - Norwalk CA
Lloyd F. Linder - Agora Hills CA
Phillip L. Elliott - Fort Collins CO
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H03K 5159
H03K 17687
US Classification:
327 94
Abstract:
A transconductance push-pull amplifier (20) generates primary push-pull currents (I1, I2) corresponding to a voltage input signal (VIN). Current mirrors (42,44) generate secondary push-pull currents (I3, I4) corresponding to the primary push-pull currents (I1, I2). For sampling, both the primary and secondary push-pull currents (I1, I2, I3, I4) are applied to charge a capacitor (C3) in a current feed-forward arrangement with high slew rate and fast signal acquisition to produce a voltage output signal (VOUT). The capacitor (C3) is disconnected from the amplifier (20) and current mirrors (42,44) to hold the output signal (VOUT). Switching transistors (Q13, Q15) which are connected between the capacitor (C3) and the current mirrors (42,44) have substantially the same non-linear modulation characteristics as corresponding output transistors (Q7, Q8) in the amplifier (20). The output and switching transistors (Q7, Q8, Q13, Q15) are connected to modulate out-of-phase such that non-linear modulation of the primary push-pull currents (I1, I2) by the output transistors (Q7, Q8) is canceled by non-linear modulation of the secondary push-pull currents (I3, I4) by the switching transistors (Q13, Q15), and the output signal (VOUT) is a highly linear replica of the input signal (VIN).

Symmetrical Bipolar Bias Current Source With High Power Supply Rejection Ratio (Psrr)

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US Patent:
53152310, May 24, 1994
Filed:
Nov 16, 1992
Appl. No.:
7/976760
Inventors:
Lloyd F. Linder - Agora Hills CA
Dwight D. Birdsall - Norwalk CA
Kelvin T. Tran - Carson CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
G05F 326
US Classification:
323315
Abstract:
A bandgap reference voltage source (104) has positive and negative terminals (104a,104b) which are connected through high impedance constant current sources (124c,126c) to positive and negative voltage supplies (+VDD,-VEE) respectively. The effect of variations of the voltage supplies (+VDD, -VEE) on the voltage source (104) is low due to the high impedances of the currents sources (124c,126c), providing a high power supply rejection ratio (PSRR). The reference voltage (VREF) generated by the voltage source (104) is converted into a reference current (IREF) which flows through two equal series resistors (108,110), and also through current mirrors (124,126) which produce positive and negative output currents corresponding thereto. The current sources (124c,126c) for the voltage source (104) are also controlled by the current mirrors (124,126). A servo control amplifier (232) senses the voltage at the junction (234) of the resistors (108,110) and adjusts the voltage at either the positive or negative terminal (104a,104b) of the voltage source (104) to maintain the voltages at the terminals (104a,104b) symmetrical with respect to ground, thereby preventing the voltage source (104) from latching to one of the voltage supplies (+VDD,-VEE) during startup.

Single-Ended And Differential Transistor Amplifier Circuits With Full Signal Modulation Compensation Techniques Which Are Technology Independent

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US Patent:
53431634, Aug 30, 1994
Filed:
Jun 21, 1993
Appl. No.:
8/080269
Inventors:
Lloyd F. Linder - Agora Hills CA
Dwight D. Birdsall - Norwalk CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H03F 345
US Classification:
330252
Abstract:
A compensating transistor (Q5) is connected in series with the collector of a main transistor (Q3), and a level shifted replica (Vin+V1) of an input signal (Vin) is applied to the base of the compensating transistor (Q5) to maintain a constant voltage difference between the base and collector of the main transistor (Q3) and compensate for base width modulation. DELTA. Vce. A voltage-controlled current source (S1) is responsive to the input signal (Vin) and applies a compensating current. DELTA. Iload which is equal and opposite to the load current variation caused by a change (. DELTA. Vin) in the input voltage (Vin) to the emitter of the main transistor (Q3) to compensate for load current modulation. DELTA. Vbe. Alternatively, the compensating current can be applied to the junction of the base of the main transistor (Q3) and the emitter of pre-distortion transistor (Q4) which has a base connected to receive the input signal (Vin). Another compensating transistor (Q12) applies a current (. DELTA.

Single-Ended And Differential Amplifiers With High Feedback Input Impedance And Low Distortion

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US Patent:
54102740, Apr 25, 1995
Filed:
Mar 17, 1994
Appl. No.:
8/210269
Inventors:
Dwight D. Birdsall - Norwalk CA
Phillip L. Elliott - Loveland CO
Lloyd F. Linder - Agora CA
Kelvin T. Tran - Carson CA
Donald G. McMullin - Beverly Hills CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
H03F 326
H03F 345
US Classification:
330265
Abstract:
First and second current feedback transconductance amplifiers (102,104) each have a high impedance voltage input, a low impedance current input and a pair of push-pull current outputs. In a single-ended configuration, an input signal is applied to the voltage input of the first transconductance amplifier (102) and the push-pull outputs of the both transconductance amplifiers are connected through a current mirror (136,138) to a node (134) where the current outputs are summed. The node current is integrated by a capacitor (174) to produce a voltage which is amplified by a transimpedance amplifier (190) to produce an output voltage which is fed back to the voltage input of the second transconductance amplifier (104). The current inputs of the transconductance amplifiers (102,104) are interconnected by a resistor (132). The high impedance voltage inputs produce common-mode cancellation of distortion in the transconductance amplifiers (102,104) and low input shot noise.

Track And Hold Circuit With Clamp

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US Patent:
60284595, Feb 22, 2000
Filed:
Apr 20, 1998
Appl. No.:
9/063104
Inventors:
Dwight Birdsall - Fort Collins CO
Ajay Kuckreja - Fort Collins CO
Phillip Elliott - Fort Collins CO
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G11C 2702
US Classification:
327 94
Abstract:
A track-and-hold amplifier circuit capable of increasing hold mode isolation includes an input circuit to buffer an input signal coupled to a switching transistor. A clamping transistor couples to the base of the switching transistor, and a hold capacitor couples between the emitter of the switching transistor and circuit ground. A differential amplifier circuit has a first input for receiving a track signal and a second input for receiving a hold signal. When the differential amplifier circuit receives the track signal, the switching circuit closes to charge the hold capacitor. When the differential amplifier receives the hold signal, the switching transistor opens to store the voltage representative of the input signal on the hold capacitor and the clamping transistor clamps the voltage at the base of the switching transistor. Thus, the base emitter voltage of the switching transistor is zero volts, and the signal held by the hold capacitor is independent of the input signal. In addition, by using level shifters, the voltage clamped at the base of the switching transistor is substantially equal to the voltage held on the hold capacitor.
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Dwight David Birdsall from Fort Collins, CO, age ~68 Get Report