Ewa M Kubalska

6359630, Mar 19, 2002

Jun 14, 1999

09/332734

Wayne Morse - Fremont CA
Michael F. Deering - Los Altos CA
Mike Lavelle - Saratoga CA
Ewa Kubalska - San Jose CA
Huang Pan - Saratoga CA
Scott R. Nelson - Pleasonton CA

Sun Microsystems, Inc. - Palo Alto CA

G06T 1530

345620

A method and computer graphics system for clip testing using clip bits stored in a general-purpose register for each vertex of a geometric primitive. In one embodiment, a rendering unit or other processor sets bits in a clip bits register for each vertex of a geometric primitive. Each bit indicates whether the vertex is inside or outside of a clipping boundary with respect to a particular clipping plane. A frame buffer controller or other graphics processor performs clip testing on the entire geometric primitive by performing Boolean operations on the clip bits. The frame buffer controller may trivially accept or trivially reject the primitive based on the clip testing. If the primitive cannot be trivially rejected or trivially accepted, then the frame buffer controller sends an interrupt to the rendering unit. The rendering unit reads an exception register to determine that the reason for the interrupt is the need to clip the primitive. The rendering unit reads the vertices from the frame buffer controller, clips the primitive, and sends the new vertices to the frame buffer controller.

6661423, Dec 9, 2003

May 18, 2001

09/861184

Michael G. Lavelle - Saratoga CA
Ewa M. Kubalska - San Jose CA
Elena M. Ing - Sunnyvale CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1206

345572, 345531, 711201

A memory array management unit suitable for use in a computer graphics system is described. The unit is especially designed to facilitate the storage of tiles of graphics data. Alignment detection between the tiles and memory block boundaries is provided for, with misalignments resulting in the automatic decimation to produce sub-tiles and generation of multiple memory write sequences.

6704026, Mar 9, 2004

May 18, 2001

09/861185

Steven M. Kurihara - Palo Alto CA
Ewa M. Kubalska - San Jose CA

Sun Microsystems, Inc. - Santa Clara CA

G09G 1140

345629, 345614, 345545

A merge unit for the merging of tiles or arrays of pixels or samples, and suitable for use in a high performance graphics system is described. The unit may improve the utilization of memory bandwidth by combining non-intersecting tiles of pixels, and hence potentially reducing the number of storage operations to the memory.

6720969, Apr 13, 2004

May 18, 2001

09/861172

Michael G. Lavelle - Saratoga CA
Ewa M. Kubalska - San Jose CA
Yan Yan Tang - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

G09G 536

345557, 345537, 345531, 711122, 711131

An external cache management unit for use with a 3D-RAM frame buffer and suitable for use in a computer graphics system is described. The unit may reduce power consumption within the 3D-RAM by performing partial block write-back according to status information stored in an array of dirty tag bits. Periodic level one cache block cleansing is provided for during empty memory cycles.

6731292, May 4, 2004

Mar 6, 2002

10/092016

Wayne Eric Burk - San Jose CA
Ewa M. Kubalska - San Jose CA
Brian D. Emberling - San Mateo CA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1576

345519, 345520, 345531

An integrated circuit may include several components, one or more interfaces, an interconnect (e. g. , a bus), and a controller. The components may each be configured to assert a read request to read data stored externally to the integrated circuit. The interfaces may be configured to output the read request asserted by one of the components and to receive data in response to outputting the request. The interconnect may be coupled to perform one or more data transactions to transmit the data from one of the interfaces to one or more of the components. In response to the read request asserted by one of the components, the controller may inhibit performance of a read transaction initiated by the read request dependent upon a comparison of a total number of outstanding data transactions to a maximum allowable number of outstanding data transactions.

6781406, Aug 24, 2004

Mar 4, 2002

10/090481

Brian D. Emberling - San Mateo CA
Ewa M. Kubalska - San Jose CA

Sun Microsystems, Inc. - Santa Clara CA

H03K 19173

326 38, 326 16

An integrated circuit including logic for testing internal operation of the integrated circuit. The integrated circuit may comprise a plurality of internal functional blocks coupled by a plurality of internal buses. The integrated circuit may also comprise a set of test control input pins and a set of test output pins comprised on the integrated circuit. The integrated circuit may comprise selection logic. The selection logic comprises inputs coupled to various ones of the internal buses, an output coupled to the set of test output pins, and a select input coupled to receive select signals from the set of test control input pins. The selection logic is operable to select internal bus signals from an internal bus based on the select signals from the test control input pins, and the selection logic is configured to output the selected internal bus signals to the set of test output pins. The integrated circuit thus allows multiplexing of different critical internal buses so that the signals on the critical buses may be output for observation via selected test pins on the integrated circuit. The observability logic may be configured to switch slowly relative to the internal busses, and the generation of the observability logic and testing may be automated.

6795078, Sep 21, 2004

Jan 31, 2002

10/066397

Michael G. Lavelle - Saratoga CA
Ewa M. Kubalska - San Jose CA
Yan Y. Tang - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

G06G 1318

345535, 345537, 345557

A memory interface controls read and write accesses to a memory device. The memory device includes a level-one cache, level-two cache and storage cell array. The memory interface includes a data request processor (DRP), a memory control processor (MCP) and a block cleansing unit (BCU). The MCP controls transfers between the storage cell array, the level-two cache and the level-one cache. In response to a read request with associated read clear indication, the DRP controls a read from a level-one cache block, updates bits in a corresponding dirty tag, and sets a mode indicator of the dirty tag to a the read clear mode. The modified dirty tag bits and mode indicator are signals to the BCU that the level-one cache block requires a source clear operation. The BCU commands the transfer of data from a color fill block in the level-one cache to the level-two cache.

6803916, Oct 12, 2004

May 18, 2001

09/861475

Nandini Ramani - Saratoga CA
David C. Kehlet - Los Altos CA
Ewa M. Kubalska - San Jose CA
Michael G. Lavelle - Saratoga CA
Michael A. Wasserman - Redwood City CA
Kevin Tang - Union City CA
Yan Yan Tang - Mountain View CA

Sun Microsystems, Inc. - Santa Clara CA

G06T 120

345506, 345558

A system and method for rasterizing and rendering graphics data is disclosed. Vertices may be grouped to form primitives such as triangles, which are rasterized using two-dimensional arrays of samples bins. Individual samples may be selected from the bins according to different criteria such as memory bank allocation to improve utilization of the systems rendering pipeline. Since the arrays may have more bins than the number of evaluation units in the rendering pipeline, the samples from the bins may be stored to FIFO memories to allow invalid or empty samples (those outside the primitive being rendered) to be removed. The samples may then be filtered to form pixels that are displayable to form an image on a display device.