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Frank Stepniak Phones & Addresses

  • Allen, TX
  • 21311 Oakview Cir, Noblesville, IN 46038 (317) 877-3078
  • Minneapolis, MN
  • Kokomo, IN
  • Colton, TX
  • Atlanta, GA
  • Long Valley, NJ
  • 1409 Marble Falls Dr, Allen, TX 75013

Work

Position: Protective Service Occupations

Education

Degree: Associate degree or higher

Public records

Vehicle Records

Frank Frank Stepniak

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Address:
1409 Marble Fls Dr, Allen, TX 75013
Phone:
(214) 383-4755
VIN:
JHMCP26768C043971
Make:
HONDA
Model:
ACCORD
Year:
2008

Resumes

Resumes

Frank Stepniak Photo 1

Senior Member Technical Staff

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Location:
Allen, TX
Industry:
Semiconductors
Work:
Texas Instruments
Senior Member Technical Staff
Frank Stepniak Photo 2

Frank Stepniak

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Publications

Us Patents

Surface Bumping Method And Structure Formed Thereby

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US Patent:
6375062, Apr 23, 2002
Filed:
Nov 6, 2000
Appl. No.:
09/706543
Inventors:
William D. Higdon - Greentown IN
Frank Stepniak - Noblesville IN
Assignee:
Delphi Technologies, Inc. - Troy MI
International Classification:
B23K 3102
US Classification:
228214, 22818022
Abstract:
A solder bumping method and structure for fine solder bump pitches. The method makes use of a semiconductor device having an input/output pad whose surface is provided with a solderable metal layer that serves as the UBM of the solder bump. A sacrificial layer is formed on the surface of the device to surround the metal layer. A plating seed layer is then formed on the metal layer and the surrounding surface of the sacrificial layer, after which a mask is formed on the seed layer and a via is defined in the mask to expose portions of the seed layer overlying the metal layer and the sacrificial layer. A solder material is deposited on the seed layer exposed within the via. The mask is then removed, followed by removal of a portion of the seed layer that is not covered by the solder material, leaving intact that portion of the seed layer beneath the solder material. The sacrificial layer is then removed, including that portion of the sacrificial layer underlying the seed layer, such that a gap is formed between the substrate and the remaining seed layer. Finally, the solder material is reflowed to form a solder bump into which the remaining seed layer is dissolved.

Conductive Adhesive Material With Metallurgically-Bonded Conductive Particles

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US Patent:
6802446, Oct 12, 2004
Filed:
Feb 1, 2002
Appl. No.:
10/060812
Inventors:
Arun K. Chaudhuri - Carmel IN
Frank Stepniak - Noblesville IN
Matthew R. Walsh - Sharpsville IN
Assignee:
Delphi Technologies, Inc. - Troy MI
International Classification:
B23K 3100
US Classification:
2282481, 228175, 438612, 252512
Abstract:
A conductive adhesive material characterized by metallurgical bonds between electrically-conductive particles dispersed in a polymer matrix of the material. The polymer matrix has a fluxing capability when heated to reduce metal oxides on the surfaces of the particles. At least the outer surfaces of the particles are formed of a fusible material, so that sufficiently heating the conductive adhesive material will reduce metal oxides on the particles, and at least partially melt the fusible metal, enabling the particles to metallurgically bond to each other and to metal surfaces contacted by the adhesive material.

Lead-Based Solder Alloys Containing Copper

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US Patent:
6811892, Nov 2, 2004
Filed:
Aug 22, 2002
Appl. No.:
10/226370
Inventors:
Shing Yeh - Kokomo IN
Bradley H. Carter - Kokomo IN
Frank Stepniak - Noblesville IN
Scott D. Brandenburg - Kokomo IN
Assignee:
Delphi Technologies, Inc. - Troy MI
International Classification:
B23K 3526
US Classification:
428647, 428620, 428674, 2282629, 2282622
Abstract:
A tin-lead solder alloy containing copper and optionally silver as its alloying constituents. The solder alloy consists essentially of, by weight, about 55% to about 75% tin, about 11% to about 44% lead, up to about 4% silver, nickel, palladium, platinum and/or gold, greater than 1% to about 10% copper, and incidental impurities. The solder alloys contain a small portion of CuSn intermetallic compounds, and exhibit a melting mechanism in which all but the intermetallic compounds melt within a narrow temperature range, though the actual liquidus temperature of the alloys may be considerably higher, such that the alloys can be treated as requiring peak reflow temperatures of about 250Â C. or less. The intermetallic compounds precipitate out to form a diffusion barrier that increases the reliability of solder connections formed therewith.

Flip-Chip Interconnected With Increased Current-Carrying Capability

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US Patent:
6822327, Nov 23, 2004
Filed:
Jun 13, 2003
Appl. No.:
10/461318
Inventors:
Pankaj Mithal - Kokomo IN
William D. Higdon - Greentown IN
Mark W. Gose - Kokomo IN
John M. Dikeman - Kokomo IN
Frank Stepniak - Noblesville IN
Assignee:
Delphi Technologies, Inc. - Troy MI
International Classification:
H01L 2940
US Classification:
257734, 257773, 257782, 257786
Abstract:
A metal runner that improves the current-carrying capability of solder bumps used to electrically connect a surface-mount circuit device to a substrate. The runner comprises at least one leg portion and a pad portion, with the pad portion having a continuous region and a plurality of separate electrical paths leading to and from the continuous region. The electrical paths are delineated in the pad portion by nonconductive regions defined in the pad portion, with at least some of the nonconductive regions extending into the leg portion. The multiple electrical paths split the current flow to and from the solder bump, distributing the current around the perimeter of the solder bump in a manner that reduces current density in regions of the solder bump where electromigration is most likely.

Wafer-Applied Underfill Process

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US Patent:
6916684, Jul 12, 2005
Filed:
Mar 18, 2003
Appl. No.:
10/391101
Inventors:
Frank Stepniak - Noblesville IN, US
Matthew R. Walsh - Sharpsville IN, US
Arun K. Chaudhuri - Carmel IN, US
Michael J. Varnau - Russiaville IN, US
Assignee:
Delphi Technologies, Inc. - Troy MI
International Classification:
H01L021/44
US Classification:
438108, 438612, 438613, 438614, 438615, 438116, 438660, 428 418, 428 401
Abstract:
A process for underfilling a bumped die surface using a lamination step and compound film such that solder bumps on the die are exposed during lamination. The compound film comprises a first layer containing an underfill material and a second layer on the first layer. The underfill material and the second layer comprise polymer materials that differ from each other. The compound film is laminated to the die, preferably at the wafer level, so that the underfill material is forced between the solder bumps and fills spaces between the bumps but does not cover the bumps. In contrast, the second layer covers the solder bumps, but is then selectively removed to re-expose the solder bumps and the underfill material therebetween.

No-Flow Underfill Process And Material Therefor

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US Patent:
6943058, Sep 13, 2005
Filed:
Mar 18, 2003
Appl. No.:
10/391231
Inventors:
Arun K. Chaudhuri - Carmel IN, US
Derek B. Workman - Noblesville IN, US
Frank Stepniak - Noblesville IN, US
Matthew R. Walsh - Sharpsville IN, US
Assignee:
Delphi Technologies, Inc. - Troy MI
International Classification:
H01L021/44
US Classification:
438108, 438612, 438613, 438614, 438615, 438616, 438660, 438127, 438124, 438126, 257787, 257789, 257795
Abstract:
A no-flow underfill material and process suitable for underfilling a bumped circuit component. The underfill material initially comprises a dielectric polymer material in which is dispersed a precursor capable of reacting to form an inorganic filler. The underfill process generally entails dispensing the underfill material over terminals on a substrate, and then placing the component on the substrate so that the underfill material is penetrated by the bumps on the component and the bumps contact the terminals on the substrate. The bumps are then reflowed to form solid electrical interconnects that are encapsulated by the resulting underfill layer. The precursor may be reacted to form the inorganic filler either during or after reflow.

Flip-Chip Interconnect With Increased Current-Carrying Capability

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US Patent:
20050046024, Mar 3, 2005
Filed:
Oct 8, 2004
Appl. No.:
10/961446
Inventors:
Pankaj Mithal - Kokomo IN, US
William Higdon - Greentown IN, US
Mark Gose - Kokomo IN, US
John Dikeman - Kokomo IN, US
Frank Stepniak - Noblesville IN, US
International Classification:
H01L021/44
US Classification:
257734000
Abstract:
A metal runner that improves the current-carrying capability of solder bumps used to electrically connect a surface-mount circuit device to a substrate. The runner comprises at least one leg portion and a pad portion, with the pad portion having a continuous region and a plurality of separate electrical paths leading to and from the continuous region. The electrical paths are delineated in the pad portion by nonconductive regions defined in the pad portion, with at least some of the nonconductive regions extending into the leg portion. The multiple electrical paths split the current flow to and from the solder bump, distributing the current around the perimeter of the solder bump in a manner that reduces current density in regions of the solder bump where electromigration is most likely.

Integrated Circuit With Low-Stress Under-Bump Metallurgy

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US Patent:
20070029669, Feb 8, 2007
Filed:
Aug 5, 2005
Appl. No.:
11/198419
Inventors:
Frank Stepniak - Noblesville IN, US
William Higdon - Greentown IN, US
International Classification:
H01L 23/48
H01L 23/52
H01L 29/40
US Classification:
257734000
Abstract:
An integrated circuit (IC) includes a semiconductor material, electronic circuitry formed on the semiconductor material, a contact layer formed on the electronic circuitry, a final passivation layer formed on the contact layer and an under-bump metallurgy (UBM) formed on at least a portion of the final passivation layer. The contact layer includes a plurality of contacts pads for providing external access to the electronic circuitry. The final passivation layer includes a plurality of windows that extend through the final passivation layer to the contact pads. The UBM includes an aluminum layer having a thickness of about 800 angstroms to about 1200 angstroms, a nickel/vanadium (Ni/V) layer having a thickness of about 800 angstroms to about 1200 angstroms and a copper (Cu) layer having a thickness of about 800 angstroms to about 1200 angstroms.
Frank Stepniak from Allen, TX, age ~62 Get Report