Search

German S Feyh

from Boulder, CO
Age ~66
Get Report
Also known as:
German Stefan Otto Feyh, German Stefan Feyh, Garman Feyh, Markus Feyh, Stefan Feyh German, Stefan Feyhotto German, Feyh Garman
Phone and address:
1272 Bear Mountain Ct, Boulder, CO 80305
(303) 543-8646
Related to:
Lukas Feyh, 36Kimberly Jane Kelly, 76Markus Andrew Feyh, 34Gabriele Isle FeyhMckenzie O'Farrell, 35Debra Ann Feyh, 63
Connected to:
Kinati T Feyissa, 50Yasmeen N Feyjoo, 26William C Feyk, 75Jeanne L Feyko, 74Eda L Feyler, 60Lynn B Feyma, 82James R Feynman, 76Timothy A Feyo, 79Russell C Feyock, 75

German Feyh Phones & Addresses

  • 1272 Bear Mountain Ct, Boulder, CO 80305 (303) 543-8646
  • Breckenridge, CO

Work

Company: Broadcom Aug 2007 Position: Technical director

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of Colorado Boulder 1985 to 1988 Specialities: Electrical Engineering

Skills

Soc • System Architecture • Asic • Mixed Signal • Signal Processing • Digital Signal Processors • Matlab • Ic • Semiconductors • Cmos • Embedded Systems • Verilog • Algorithms • Fpga • Debugging • Analog • Hardware Architecture • Vlsi • Eda • Integrated Circuit Design • Circuit Design • Electronics • Simulations

Languages

English • German

Industries

Semiconductors

Public records

Vehicle Records

German Feyh

View page
Address:
1272 Bear Mtn Ct, Boulder, CO 80305
Phone:
(303) 543-8646
VIN:
4T1BB46K27U010093
Make:
TOYOTA
Model:
CAMRY HYBRID
Year:
2007

Resumes

Resumes

German Feyh Photo 1

Technical Director

View page
Location:
Denver, CO
Industry:
Semiconductors
Work:
Broadcom
Technical Director
Lsi Corporation 2000 - 2007
Technical Manager
Cirrus Logic Jul 1994 - Mar 2000
Senior Manager
Education:
University of Colorado Boulder 1985 - 1988
Doctorates, Doctor of Philosophy, Electrical Engineering University of Erlangen - Nuremberg 1977 - 1984
University of Colorado Boulder 1981 - 1982
Master of Science, Masters, Electrical Engineering
Skills:
Soc
System Architecture
Asic
Mixed Signal
Signal Processing
Digital Signal Processors
Matlab
Ic
Semiconductors
Cmos
Embedded Systems
Verilog
Algorithms
Fpga
Debugging
Analog
Hardware Architecture
Vlsi
Eda
Integrated Circuit Design
Circuit Design
Electronics
Simulations
Languages:
English
German

Publications

Us Patents

Zero Forcing Adaptive Equalization In A Disk Drive Read Channel

View page
US Patent:
6381085, Apr 30, 2002
Filed:
Jul 12, 1999
Appl. No.:
09/351736
Inventors:
Li Du - Denver CO
Mark Stephen Spurbeck - Superior CO
German Feyh - Boulder CO
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
G11B 5035
US Classification:
360 65, 375350
Abstract:
The invention includes disk drive circuitry, systems, and methods. The disk drive system comprises control circuitry and a disk device. The disk device stores data and transfers an analog signal representing the data. The control circuitry receives the analog signal, converts the analog signal into a digital signal, and transfers the digital signal. The control circuitry includes zero forcing circuitry and an adaptive filter. The zero forcing circuitry produces new coefficients for the adaptive filter. The control circuitry may also include an analog-to-digital converter, detector, decoder, and LMS circuitry. The analog-to-digital converter receives and samples the analog signal to generate a sampled signal. The adaptive filter shapes the sampled signal based on coefficients to produce an equalized signal. The detector detects binary data from the equalized signal, and the decoder decodes the binary data to generate the digital signal.

Reduced Recovery Time For Perpendicular Recording Systems

View page
US Patent:
7119977, Oct 10, 2006
Filed:
Mar 28, 2005
Appl. No.:
11/091352
Inventors:
James P. Howley - Broomfield CO, US
Zachary Keirn - Loveland CO, US
German Feyh - Boulder CO, US
Michael P. Straub - Longmont CO, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11B 5/02
US Classification:
360 67
Abstract:
User data is read from a medium having servo data and user data encoded thereon. The user data is read with a read/write head that is operable in a write mode and a read mode. Servo data is read in a time window following a transition from write mode to read mode, with a frequency passband that has a first low frequency corner. User data is read from the medium after expiration of the time window, with a frequency passband that has a second low frequency corner that is lower than the first low frequency corner.

Integrated Circuit And Method For Remodulating Bits And Hard Disk Drive Incorporating The Same

View page
US Patent:
7167327, Jan 23, 2007
Filed:
Jan 6, 2003
Appl. No.:
10/337071
Inventors:
German S. Feyh - Boulder CO, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
G11B 5/09
US Classification:
360 46, 360 51
Abstract:
A remodulator embodied in an integrated circuit (IC), a method for remodulating bits and a controller and disk drive incorporating the IC or the method. In one embodiment, the IC includes: (1) a remodulator that processes incoming bits to yield remodulated outgoing bits, the remodulator including a selected one of a decision feedback loop and an error feedback loop and (2) a feedforward loop coupled to an input of the remodulator and having a baseline wander filter, the baseline wander filter cooperating with the selected one of the decision feedback loop and the error feedback loop to reduce a bit error rate of the remodulated outgoing bits.

Data Detection And Decoding System And A Method Of Detecting And Decoding Data

View page
US Patent:
7421643, Sep 2, 2008
Filed:
Jan 4, 2005
Appl. No.:
11/029148
Inventors:
Hongwei Song - Boulder CO, US
German Feyh - Boulder CO, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H03M 13/00
US Classification:
714794
Abstract:
A data detection and decoding system in which a single parity bit added to the end of each code word by the encoder is used in the channel detector to improve the accuracy with which bit decisions are made in the channel detector. The bit estimates and the reliability estimates are then processed by the decoder to recover the original input bits. By using single parity for this dual purpose in combination with a decoder that follows the channel detector and uses the bit estimates and reliability estimates to recover the original input bits, performance of the data detection and decoding system is greatly improved while also overcoming the disadvantages of known digital recording systems.

Format Efficient Timing Acquisition For Magnetic Recording Read Channels

View page
US Patent:
7529320, May 5, 2009
Filed:
Sep 16, 2005
Appl. No.:
11/228762
Inventors:
Jason Byrne - Lyons CO, US
German Feyh - Boulder CO, US
Jeffrey Grundvig - Loveland CO, US
Aravind Nayak - Longmont CO, US
Richard Rauschmayer - Longmont CO, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04L 27/00
US Classification:
375326, 375316
Abstract:
A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.

Conditionally Input Saturated Viterbi Detector

View page
US Patent:
7876862, Jan 25, 2011
Filed:
Jul 16, 2007
Appl. No.:
11/778177
Inventors:
Hao Zhong - Bethlehem PA, US
German Feyh - Boulder CO, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04L 27/06
H03D 1/00
H03M 13/03
US Classification:
375341, 375340, 375262, 714794, 714795
Abstract:
Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a decoder including a branch metric calculator that conditionally calculates a branch metric based on either an actual input or a saturated input. Such a branch metric calculator is operable to receive an actual input, and to compare the actual input with an expected range. At times, the aforementioned comparison yields a comparison result indicating that the actual input is outside of the expected range. A first branch metric associated with a first branch is calculated. Where the first branch has an expected value representing a boundary of the expected range, calculating the first branch metric is done using the saturated input. Further, a second branch metric associated with a second branch is calculated. Where the second branch has an expected value representing something other than a boundary of the expected range, calculating the second branch metric is done using the actual input.

Timing Error Recovery System

View page
US Patent:
20050169415, Aug 4, 2005
Filed:
Jan 31, 2005
Appl. No.:
11/047377
Inventors:
Aravind Nayak - Longmont CO, US
German Feyh - Boulder CO, US
Assignee:
Agere Systems Inc. - Allentown PA
International Classification:
H04B017/00
US Classification:
375355000
Abstract:
A timing error recovery system includes a phase locked loop that receives a continuous time input signal, samples the input signal at a sampling rate and generates a voltage control signal. A statistical estimator, such as a maximum a posteriori estimator, compares the voltage control signal with an expected error based upon a statistical model and produces an adjusted voltage control signal that drives a voltage controlled oscillator to adjust the sampling rate.

System And Method For Un-Interrupted Operation Of Communications During Interference

View page
US Patent:
20110103459, May 5, 2011
Filed:
Apr 30, 2010
Appl. No.:
12/771722
Inventors:
Tooraj ESMAILIAN - Irvine CA, US
Scott POWELL - Newport Beach CA, US
Chung Ming TU - Irvine CA, US
KuoRuey HAN - Irvine CA, US
Kadir DINC - Irvine CA, US
German FEYH - Boulder CO, US
Assignee:
Broadcom Corporation - Irvine CA
International Classification:
H04B 1/10
H03K 5/159
US Classification:
375233, 375350
Abstract:
Methods and systems to substantially eliminate effects of EMI burst noise in an Ethernet system are provided herein. The method includes the step of computing and storing filter coefficients configured to adapt to a range of EMI frequencies. The method further comprises the step of receiving a signal and detecting EMI and frequency of the EMI in the received signal. The method further comprises selecting filter coefficients corresponding to the determined frequency of the detected EMI and adjusting a frequency response of one or more filters using the selected filter coefficients so as to substantially eliminate effects of the EMI in the received signal. The method further includes the step of sending filter coefficients to a link partner corresponding to the frequency of the detected EMI.
Control profile
German S Feyh from Boulder, CO, age ~66 Get Report