Search

Zhan H Chen

from Millbrae, CA
Age ~41
Get Report
Also known as:
Zhan Hang Chen, Hang Chen Zhan, Harry Chen, Zhanhang Chen, Chen Zhan
Related to:
Harry ChenZhang ChenChi C Zhan, 41Wei G ChenCui Chen, 50
Connected to:
Adela Chen, 45Aidong Chen, 56Aile Chen, 40Aiqun Chen, 56Aishun Chen, 46Aiting Chen, 39Albertina L Chen, 78Alec C Chen, 60Allison Y Chen, 42Andrea H Chen, 40

Zhan Chen Phones & Addresses

  • Millbrae, CA
  • 665 Victoria St, San Francisco, CA 94127
  • 363 Woodrow St, Daly City, CA 94014 (415) 318-9917

Work

Company: Wilson Sonsini Goodrich & Rosati Professional Corporation Address:

Specialities

Mergers & Acquisitions • Corporate Finance • Corporate Law & Governance

Professional Records

Lawyers & Attorneys

Zhan Chen Photo 1

Zhan Chen - Lawyer

View page
Office:
Wilson Sonsini Goodrich & Rosati Professional Corporation
Specialties:
Mergers & Acquisitions
Corporate Finance
Corporate Law & Governance
ISLN:
917039421
Admitted:
2003
University:
Shanghai International Studies University, B.A., 1993; Sunny Buffalo, M.A., 1998
Law School:
Columbia Law School, J.D., 2002

Resumes

Resumes

Zhan Chen Photo 2

Member Of Technical Staff

View page
Location:
1520 Byp 2 Hwy east, Minot, ND
Industry:
Computer Software
Work:
Pure Storage
Member of Technical Staff
Pure Storage May 2016 - Aug 2016
Linux Kernel Engineering Intern
Carnegie Mellon University Jan 2016 - May 2016
Teaching Assistant
Nicta Oct 2014 - Apr 2015
Intern Supervised By Professor Kevin Elphinstone and Professor Gernot Heiser
Education:
Carnegie Mellon University 2015 - 2016
Master of Science, Masters, Computer Science Zhejiang University 2011 - 2015
Bachelor of Engineering, Bachelors, Computer Science
Skills:
C
Operating Systems
Go
Zhan Chen Photo 3

Software Engineer

View page
Location:
San Francisco, CA
Industry:
Internet
Work:
Google
Software Engineer
Education:
Rutgers University 2013 - 2016
Master of Science, Masters, Computer Engineering University of Electronic Science and Technology of China 2010 - 2014
Bachelors, Bachelor of Science, Communications, Electronics Engineering, Engineering, Electronics
Skills:
C++
Java
Matlab
Research
Python
Javascript
Distributed Systems
Parallel Programming
Teamwork
Web Design
Databases
Openmp
Hadoop
Mpi
Cuda
Git
Multi Threaded Programming
C
Zhan Chen Photo 4

Engineering Manager

View page
Location:
Sunnyvale, CA
Industry:
Computer Software
Work:
Netflix
Engineering Manager
Netflix
Senior Software Engineer
Yahoo Mar 2006 - Oct 2011
Senior Software Engineer
Huawei Technologies Jul 1998 - Jul 2001
Software Engineer
Education:
Shanghai Jiao Tong University
Bachelor of Engineering, Bachelors, Communication, Engineering Iowa State University
Master of Science, Masters, Computer Science
Skills:
Commerce
E Commerce
Software
Zhan Chen Photo 5

Zhan Chen

View page
Zhan Chen Photo 6

Zhan Chen

View page

Publications

Us Patents

Low-Temperature Catalyzed Formation Of Segmented Nanowire Of Dielectric Material

View page
US Patent:
20070004225, Jan 4, 2007
Filed:
Jun 30, 2005
Appl. No.:
11/174076
Inventors:
Donghui Lu - San Jose CA, US
Zhan Chen - Aurora IL, US
International Classification:
H01L 21/469
US Classification:
438778000, 438792000, 977762000, 977891000
Abstract:
The present invention discloses a method of forming a segmented nanowire including: providing a substrate; pre-cleaning the substrate; pre-treating the substrate; forming and placing a catalyst over the substrate; and forming the segmented nanowire over the catalyst with recurring pulses of plasma-enhanced chemical vapor deposition (PECVD) of a dielectric material.

Low-Temperature Catalyzed Formation Of Segmented Nanowire Of Dielectric Material

View page
US Patent:
20090093131, Apr 9, 2009
Filed:
Dec 5, 2008
Appl. No.:
12/315733
Inventors:
Donghui Lu - San Jose CA, US
Zhan Chen - Aurora IL, US
International Classification:
H01L 21/31
US Classification:
438778, 257E2124, 977762
Abstract:
The present invention discloses a method of forming a segmented nanowire including: providing a substrate; pre-cleaning the substrate; pre-treating the substrate; forming and placing a catalyst over the substrate; and forming the segmented nanowire over the catalyst with recurring pulses of plasma-enhanced chemical vapor deposition (PECVD) of a dielectric material.

Design Rule Correction System And Method

View page
US Patent:
61891320, Feb 13, 2001
Filed:
Apr 9, 1998
Appl. No.:
9/057961
Inventors:
Zhan Chen - Santa Clara CA
Gustavo E. Tellez - Cornwall on Hudson NY
John Cohn - Richmond VT
Rani Narayan - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1750
US Classification:
716 11
Abstract:
A method of modifying a layout of a plurality of objects in accordance with a plurality of predetermined criteria is presented. An objective function is defined for measuring a location perturbation and a separation perturbation of the objects in the layout. A linear system is defined using linear constraints in terms of design rules and the objective function to describe separations between layout objects. The linear system is solved to simultaneously remove violations of the design rules, and shapes and positions of objects in the layout are modified in accordance with the solution of the linear system such that a total perturbation of the objects in the layout is reduced. A system for implementing the present invention is also presented.

Granular Voltage Tuning

View page
US Patent:
20210255927, Aug 19, 2021
Filed:
Apr 16, 2021
Appl. No.:
17/233097
Inventors:
- Mountain View CA, US
Gordon James Coleman - Los Altos CA, US
Douglas Lother - Mountain View CA, US
Zhan Chen - Santa Clara CA, US
International Classification:
G06F 11/14
G06F 11/16
G06F 11/10
G11C 29/00
G06F 12/1009
Abstract:
A system and related method operate solid-states storage memory. The system performs a first tuning process that has a first set of tuning options, on a first portion of solid-states storage memory. The system identifies one or more second portions of solid-states storage memory, within the first portion of solid-states storage memory that fail readability after the first tuning process. The system performs a second tuning process that has a differing second set of tuning options, on each of the one or more second portions of solid-states storage memory.
Control profile
Zhan H Chen from Millbrae, CA, age ~41 Get Report